Design, Test & Repair Methodology for FinFET-Based Memories
Dr. Yervant Zorian, Chief Architect and Fellow, Synopsys
The advent of FinFET-based memories presents new memory test challenges. This white paper covers the new design complexities, defect coverage and yield challenges presented by FinFET-based memories; how to synthesize test algorithms for detection and diagnosis of FinFET specific memory defects; and how incorporating built-in self-test (BIST) infrastructures with high-efficiency test and repair capabilities can help to ensure high yield for FinFET-based memories.

If you wish to download a copy of this white paper, click here
|
Synopsys, Inc. Hot IP
Related Articles
New Articles
- Analysis and Summary on Clock Generator Circuits and PLL Design
- Understanding why power management IP is so important
- Hardware-Assisted Verification: The Real Story Behind Capacity
- Bigger Chips, More IPs, and Mounting Challenges in Addressing the Growing Complexity of SoC Design
- SoC design: What's next for NoCs?
Most Popular
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |