Mark Peryer, Mentor Graphics
EDN (December 21, 2015)
Most electronics systems use memory components either for storing executable software or for storing data, and therefore the availability of accurate memory models is fundamental to most functional verification strategies. Making these models available in proven, standards-based libraries is essential. This article describes the qualities you should look for in such models and introduces a new library that I feel delivers the most comprehensive solution of this kind and supports any type of simulation environment and all three of the industry-leading simulators.
Memory model requirements
For verification modelling purposes a memory device can be abstracted as a signal-level protocol interface to a storage array. The signal-level interface has to conform to the timing and behavior of the memory protocol, which may be specified in an industry standard, such as the JEDEC JES79-3F standard for DDR3 or, in a specific case, it may be described in a device manufacturer’s datasheet. How the storage array is implemented is not directly visible to the user, but for simulation models it is generally implemented using either a SystemVerilog data structure or an optimized C data structure.
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