FPGA Design: Faster Runtimes & Increased Productivity

Joe Mallet, Synopsys
EETimes (1/13/2016 04:40 PM EST)

In order to achieve accelerated FPGA development schedules, designers require the aid of sophisticated synthesis tools.

FPGA device density is continuing to grow at approximately 2x per node, which is -- not surprisingly -- driving larger, more complex designs. This means that FPGA designers face several challenges as follows:

Longer run times due to increasing design size and complexity.
Achieving rapid synthesis turn-around time to integrate design changes.
Avoiding unnecessary resynthesizing of pre-verified, static modules, like IP blocks and completed modules.

In order to achieve accelerated FPGA development schedules, while supporting increasing design sizes and complexity, designers require the aid of sophisticated synthesis tools.

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