Qian Yu, Technical Marketing Manager at ARM
The volume of products and applications being developed for the Internet of Things (IoT) is growing fast; and consequently, demand for IoT application SoCs is high. This is especially the case for end-point devices such as sensor nodes and Wi-Fi and Bluetooth ‘Smart’ Low-Energy (BLE) based radios and networks. These are found in a myriad of applications including audio/voice processing, environment monitoring sensor hubs and especially energy-harvesting systems. Many of these applications will need to be powered with low-density, coin-cell-type batteries that will need to last months or years, rather than hours or days as we might expect for our smartphones and other personal consumer devices.
Clearly, this means there will be stringent requirements for energy consumption, and one method of achieving this level of low energy consumption lower voltage operation is to reduce active and leakage current consumption to reach the minimum energy point (MEP).
The goal for ARM, indeed for the industry, is to enable semiconductor makers and SoC designers to achieve the lowest possible power consumption and longest battery-life for IoT end-point devices. ARM believes that the development of market-leading physical IP based on near-threshold technology can make this possible.
ARM has already carried out several advanced R&D projects looking at the operation of near-threshold (500-700mV), sub-threshold (350-500mV) and deep-sub-threshold (less than 350mV) voltages. A key element of these experiments was to determine the voltage that results in the minimum energy required to complete a computational task, while not exceeding the peak current limit. In reality, the lowest possible voltage does not correspond to the optimal or minimum energy point (see figure 1), as the combination of active and leakage power at very low voltages may result in higher energy consumption. As the voltage drops to near or below the threshold, leakage power will actually increase rather than decrease. Another aspect is that as the voltage drops, more time is required to complete a task, also leading to an increase in leakage.
Figure 1 – The minimum energy point (MEP) is not necessarily achieved at the lowest possible voltage, due to the combination dynamic/switching energy and increasing leakage energy at low voltages
Statistical models for today’s PDKs (Process Design Kits) available from the major foundries are typically optimised around 1V to 0.9V and are robust and accurate. However, simulations have shown that the typical Gaussian distribution model for transistors will break down at lower voltages. Process rules at TSMC, for example, do not guarantee operation any lower than 20% below the process domain’s nominal voltage. It is clear that to enable near-threshold design, foundries will need to optimise their processes at lower voltages by creating more accurate models and reduce the statistical variation at near-threshold voltages. Another issue is whether the assumptions of current EDA tools, such as timing closure tools, will apply the correct statistical model for analysis at the near-threshold operating voltage. The tool in question may make the assumption that the user library only operates at +/–20% of the voltage domain constrained by the foundry process rules.
In addition, the standard cell architecture will require an element of restructuring, as some sequential cells such as stacked cells will not work at near-threshold voltage. In conjunction with this standard cell optimization, there will be other implementation issues that will need to be looked at, such as on-chip regulation. This will most likely mean that new circuit-design techniques will need to be introduced to optimize near-threshold logic. However, there will need to be trade-offs in terms of area, power and performance.
Finally, there is the issue of memory. Whereas logic is perhaps more straightforward, memories, especially embedded SRAM, will require higher voltages for read/write operations and to retain stored values. Higher-level voltage shifting will be required for more complex designs with memory surrounded by lower-voltage-level logic. In addition, it can be foreseen that there will be the requirement for the development of larger customized memory bitcells, resulting in larger area memories, there will need to be a trade-off in terms of achieving the ideal minimum energy point versus stability of the memory bitcell.
Given all these issues faced in design, implementation and silicon testing with standard EDA tools and IP abstractions, ARM has concluded that near-threshold IP can be productised despite these challenges.
The company has already developed many logic IP libraries that have multiple operating voltage domains supported in 55nm down to the 14nm process node. It is now developing prototype libraries based on the latest foundry PDKs for near-threshold operation for 55nm and 40nm processes, which today are the sweet spot for the development of IoT end-point devices. Leading EDA vendors and foundries are already preparing to support the introduction of near-threshold technology.
ARM is now working on the fabrication of a proof-of-concept, near-threshold-technology test chip, with expected tape-out in the first half of 2016. While this development is a short- to intermediate-term solution, it should be an important step in the evolution to enable true near-threshold design that is based on the minimum energy point.
In reality, IoT end-point SoCs will not necessarily have to be implemented in their entirety in near-threshold technology. Certain logic blocks, such as the monitoring elements of IoT subsystems or audio processing blocks where high-performance processing is not a requirement, can certainly benefit from near-threshold operation. Other blocks that require higher speed or performance can be implemented with standard cell logic operating at 1.0V or 0.9V.
Based on current foundry models and the latest design tools and libraries, it is should be possible to create new near-threshold voltage design capabilities. Certainly there are some major challenges: these include the availability of robust and stable low-voltage process technologies, EDA tools support, issues of memory integration into low-power SoC designs, and the lack of leading-edge near-threshold physical IP products. However, it should be possible in the near future to enable true near-threshold design – based on the minimum energy point rather than the lowest possible voltage – to enable the next generation of SoCs for end-point IoT products and systems.