By Sierene Aymen and Hartmut Marquardt, Mentor Graphics
Eliminating manual work during power intent verification of analog IPs reduces susceptibility to risks created by human error.
Creating macro power models for analog intellectual property (IP) blocks is essential to enable the chip assembly group to effectively integrate these blocks within their place and route environment. These macro models, which define power domains, identify IP ports as signal, power, ground, or trivial ports, and describe the associations of signal pins to power supply pins. Due to their complexity, and the unlimited design freedom of full custom designs, there is no algorithmic solution for the automated generation of these macro power models, so they must be developed manually by designers. However, that leaves them susceptible to human mistakes and oversight. Errors in these power models can have a wide array of possible effects on the circuitry, from slight performance effects to extreme damage to the IPs.
However, developing an automated flow for power intent verification is not only possible, but practical. By automating the verification of macro power models we can at least find and eliminate any errors in a timely and accurate manner during circuit qualification.
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