Joe Mallett, Synopsys
EETimes (4/11/2016 01:20 PM EDT)
A versatile, iterative, and incremental debug methodology allows FPGA designers to deliver debugged designs quickly and easily ensuring design integrity and robustness.
FPGA device density is continuing to grow at approximately 2x per node, which is driving the ability for FPGAs to incorporate more of the system design into the devices. This means that companies designing new FPGA-based products continue to drive higher integration and, subsequently, more complexity into their system designs. This has led companies designing complex FPGAs to move increasingly toward licensing IP cores for the majority of the building blocks of their designs, as opposed to building their own in-house custom versions.
FPGA designers typically use IP from multiple sources ranging from internal to FPGA device vendors. In order to efficiently leverage IP from multiple sources, designers require synthesis and debug tools that support the portability of IP across technologies, along with the ability to properly handle the various forms of IP. The Synplify synthesis tools automate much of the handling of design IP by directly supporting vendor IP catalogs like Altera's Megawizards and Xilinx's IP catalog.
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