By David Axelrad, Cadence
High-speed SerDes interfaces are the gateway for data traffic and analysis on the cloud. End-users want a faster connection to their data. They want to download and stream HD movies as fast as possible. They also want to seamlessly share huge databases. This need for speed directly drives SerDes innovation. In the datacenter market and in the enterprise market, it’s extremely important to have a fast connection.
Power is also very important—users want their phones to last at least one day per charge. They want to make that last phone call to customers. And they want discrete wearables to be able to monitor their exercise activity throughout the day.
Everyone knows the stress of not having enough battery life for their device. But it is also of critical importance in the datacenter, because one of the top priorities of the IT cloud manager is to monitor energy cost and to lower the total consumption of the datacenter.
Because battery life is the specification that most matters to consumers, we need to come up with a new architecture that enables even lower power modes to enable a SerDes with the power to scale with the data rate. Plus, the architecture must have a minimum exit latency, because users want their devices to wake up immediately when they need them.
Figure 1: Battery life – the only specification that really matters!
Another trend is the consolidation of connectors and cables. The main impact is a reduction of the external ports on devices, enabling more ergonomic form factors, and to reduce the number of cable users carry every day and increase the ease of connectivity. To make this consolidation a reality will require converging the transmission of data, power, and video.
We in the SerDes community have made tremendous progress in the last decade in terms of SerDes speed. Between 2005 to 2012, we moved from 10Gbps to 28Gbps, and we saw the introduction of 56Gbps SerDes only 3 years later. How did this happen? How did we increase the speed of innovation, doubling the rate in seven years, and then again in just three years? One of the key achievements of the engineering community is that we all have decided to move to a new modulation format—from traditional NRZ to PAM 4—which unleashed our creativity as SerDes designers and enabled the introduction of new architectures to reach those data rates.
Figure 2 – PAM 4 breaking the barriers of SerDes speeds
The key question may be “What is next?” How and when are we going to move from 56Gbps to 112Gbps? Will the SerDes that we know today, with the architecture we know today, be the same in the future? Or must the underlying technology change (e.g., maybe silicon photonics)?
The same question arises at the datacenter level. We need 56Gbps SerDes that scales in terms of power, and the power must scale with the data rate so we can operate efficiently even at 10Gbps.
Connector consolidation is a trend on the move, to one connector—one SerDes. Today’s best example is USB Type-C™ ramping in the market. Via the USB Type-C connector and a single cable, we can transmit data, we can transmit video through DisplayPort, and we can transmit up to 100W of power. This consolidation radically enhances the cable connectivity options for users, increasing flexibility and simplifying at the same time. And the connector is reversible, addressing one of the most vexing USB experiences of flipping the plug. It’s a different kind of SerDes innovation, but crucial for the industry.
Figure 3: One connector—One SerDes
In conclusion, we SerDes designers and product managers have a very bright future ahead of us, as the benefits for the end user are directly driving our daily life. Yet, we need to understand and listen to our customers, we need to understand their priorities. At Cadence, we strive to listen and innovate.
About the Author
David Axelrad is a senior principal product marketing manager at Cadence responsible for High-End SerDes (16G, 32G & 56G). He has a PhD in electrical engineering and an MBA in Innovation Management. Before Joining Cadence, David was technical product marketing manager for networking ASIC. He drove development of leading edge technologies including high speed SerDes (28/56G, PAM4) and silicon photonics.