Chris Allsup, Synopsys
EETimes (8/10/2016 05:55 PM EDT)
New semiconductor technologies like FinFETs are giving rise to new types of fault effects not covered by standard stuck-at and at-speed tests.
Automatic test pattern generation (ATPG) tools perform two key functions: (1) they generate stimulus/response patterns used by automatic test equipment (ATE) to determine whether or not a digital or mixed-signal design is defective, and (2) if the design is defective, they isolate the probable location of the fault(s). For decades, ATPG has proven a reliable workhorse in performing these functions, but now a young, sleek stallion has come to pasture -- in order to accommodate recent trends in the semiconductor industry, Synopsys has re-engineered ATPG from the ground up to be smarter and more efficient.
One of these trends is the growing deployment of FinFET process technology for SoC designs. Though opinions differ on whether FinFET intrinsically requires special testing versus FDSOI or other MOSFET technologies, the circuit dimensions are so small (16nm or less) that on-chip process variations can affect transistor sizes, threshold voltages, and wire resistances. These variations give rise to new types of fault effects not covered by standard stuck-at and at-speed tests.
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