Verification "escapes" leave bugs in silicon

Bipin Patel & Manzil Shah (eInfochips)
EDN -- September 12, 2016

For many years, design verification has been the biggest challenge for any company involved in ASIC design. To address verification challenges for increasing complexity in ASIC designs, over the period of the last couple of decades, various hardware verification languages (HVLs) have emerged. Starting with Verilog as a basic verification language around 2000, various HVLs like Open Vera and System Verilog have gained popularity.

The semiconductor industry has widely adopted System Verilog as an effective and user-friendly HVL. EDA companies come up with something new every few years to speed up and add value to the verification cycle of an ASIC design. Like HVLs, various methodologies, like eRM, AVM, VMM, OVM, and UVM have become popular in the span of a few years. UVM is the most popular verification methodology that the industry has adopted widely for SV as an HVL. Formal verification techniques are also gaining popularity these days as related tools mature.

Now, the question that emerges here is, in spite of having powerful HVLs, metrologies, and good verification practices in place, ASIC design companies face verification escapes – bugs missed in design validation/verification – for certain scenarios that get caught during the silicon validation phase, or while using the end product at the customer end. Such escapes lead to a respin of the ASIC, which is of course very expensive as far as the product cost and time-to-market is concerned. Sometimes, the company has to go with multiple respins of the ASIC if new issues are caught after a respin is done and a hardware or software workaround is not possible. This paper discusses some causes that lead to silicon bugs.

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