by Umesh Patel and Dhaval Shah, Arastu Systems Pvt. Ltd.
The need for intelligent verification is the outcome of a two decade long pre-silicon verification process. Intelligent testbench automation, which is a supplement of intelligent verification, is a step closer towards achieving more confidence in design with minimal engineering effort. Applications today demand diverse functionality, which results in complex to very complex designs. Pre-silicon verification for first-pass success using current verification approaches is just not enough. A unique approach is needed that not only verifies the design faster but also achieves consistent results. Intelligent testbench with automation is the answer to today’s manual verification approach.
ASICs today demand high-bandwidth operations; which in turn demand high bandwidth on a system memory bus, like a DRAM interface bus. It is imperative that a comprehensive verification plan also includes verification for performance and power along with functional features. Having a large number of variables makes verification more complex. But this adds confidence in ASIC/SoC completeness for an end user’s application. In order to achieve high system performance in any ASIC/SoC, DRAM bus bandwidth utilization is equally important for that system.
High bandwidth on DRAM means less idle DRAM cycles. Manually finding coverage holes in the verification of a DRAM bus is a tedious process. This article proposes a unique verification component that helps find these holes in an intelligent manner, and it discusses potential solutions and advantages over other verification approaches. Additionally, it proposes another intelligent component which helps in simulating real-world fault/error cases without waiting for a chip to get fabricated and tested and also discusses achieving seamless portability across all memory sub-systems.
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