By Colin Osborne and Peter Hawkins
It sounds trite, but it’s always true: The stakes are higher in system-on-chip (SoC) design than ever. And tomorrow they’ll be even higher.
In a globally competitive electronics environment, functionality is no longer enough in ever-more complex SoCs. It is essential to achieve performance and power requirements and it’s crucial to hit schedule and budget requirements at the same time. An under-designed SoC may run too slowly to keep up with the demands of the system. An over-designed SoC will consume too much power and require more expensive IP blocks. Blow up the power budget (or the cost budget) and your device might not be competitive; slip schedule by a month and you might miss the market window.
It is often too late to analyze and resolve such issues once silicon has been produced. It is therefore important for analysis and optimization to be considered from a very early stage in the design life cycle.
We think it’s crucial to start early, analyzing IP and systems using a number of techniques and at several levels. The aim of performance analysis, therefore, is to prove and improve the performance and power efficiency of ARM-based systems.
Typically, an SoC is a heterogeneous system and contains blocks that generate different types of traffic. All these blocks compete for the same memory and interconnect resources. The backplane (Memory Subsystem and Interconnect) must be intelligent enough to resolve contention of resources between different IP blocks and handle different types of traffic efficiently and fairly.
Some of the factors that affect system performance include:
- Processor speed (CPU, GPU, Video, Display etc.)
- Cache types and sizes
- Memory speed, efficiency and data width
- Optimal integration of the blocks
Making use of Advanced System IP and tools allows designers to select interconnect topologies, DMCs, SMMUs and GICs. It also places solutions such as hardware-managed cache coherency and dynamic end-to-end quality of service at their disposal.
It is important that the configuration options chosen by designers satisfy a multi-dimensional problem, affecting the performance of each function as well as the physical size and power dissipation.
Designers need answers to several questions at an early stage of the design process:
- What functions should be implemented in hardware or software?
- Which ARM processors (CPU, GPU…) should be used? or can the chosen processor(s) handle the software functions within the real-time constraints of the system?
- What is the internal bus utilization between the processor and other IP?
- What is the worst-case interrupt latency?
- What is the expected system power consumption for its proposed use cases
To address these challenges and help designers with the optimal system configuration, ARM executes extensive performance analysis work.
ARM conducts this analysis at various levels of abstraction from; static analysis, dynamic modeling, RTL simulation, RTL emulation, FPGA and silicon. Levels will start from IP up to system integration, and hardware only up to OS software and hardware.
And just like working in the pits of a Formula 1 race – it is important to find the right balance in system design, as it can lead to massive gains in performance.
To get even more insight into ways performance analysis can optimize your design, download our white paper and sign up for our Reference Data webinar in January.
(Colin Osborne is senior engineering manager at ARM; Peter Hawkins is principal engineer in ARM’s Systems and Software Group).