Ron Wilson, Intel FPGA
It is no news that power design for modern systems is hard. The escalating demands of advanced chips—huge bursts of current, multidecade operating ranges, fast transients, and digital mode controls—have turned supplying power at the point-of-load (PoL) from an exercise in arithmetic into an adventure in high-bandwidth mixed-signal design. Looking in the opposite direction, pressure for greater plant-level efficiency is pushing really high DC voltages—48V and more—from the bottom of the rack or the back of the chassis closer and closer to the CPUs and SoCs. Caught in the middle, power designers must somehow produce a mixed-signal network and not a train wreck.
The Supply Side
The challenges start out with the bulk DC regulators. In aircraft, 28 VDC has long been the de-facto standard. In hybrid and electric vehicles, several hundred VDC may be available at the battery. Telco or server racks may be distributing anything from the traditional 12 VDC to 48V.
Normal practice says you step these high voltages down for distribution to individual circuit boards. But if the system is large or efficiency is a vital concern, multiple layers of buck regulators may not be the best choice. Efficiency dictates that you push the high DC voltage as deep into the system as you can.
Some designers talk about powering PoL regulators directly from 48V. In a recent presentation, Google claimed their 48V rack architecture reduced distribution losses by a factor of 16 compared to 12V racks. The Google approach fed 48V directly to the PoL regulators handling big loads like CPUs or DRAM arrays, while stepping down the bulk voltage to 12V to supply more complex requirements with specialty regulators.
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