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130nm OTP Non Volatile Memory for Standard CMOS Logic Process
Debugging hard faults in ARM Cortex-M0 based SoCs
Shashikant Joshi & Hanumanthaiah Shruti (Cypress Semiconductors)
embedded.com (February 08, 2017)
Programmable system-on-chip (PSoC) architectures integrate a wide range of capabilities, including MCU cores like the Cortex-M0, programmable analog blocks (PAB), programmable digital blocks (PDB), programmable interconnect and routing, a wide range of interfaces and peripherals, and advanced capabilities such as capacitive touch sensing. These architectures over many advantages over traditional microcontrollers and can substantially reduce design time and system bill of materials (BOM) cost.
As the complexity of programmable system-on-chip architectures and their MCU increases, so do the issues that can occur at each stage of design. One common issue developers face in Cortex-M0-based embedded systems is the hard fault. In some cases, we might get lucky and be able to quickly locate the source of the hard fault. However, most of the time chasing down a hard fault can be very time consuming. In this article, we will discuss some common errors programmers make and how to debug the hard fault caused by these errors.
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