Adam Taylor, E2V
embedded.com (February 22, 2017)
During the course of my career, I have been involved with developing a number of FPGA designs for some really interesting projects. Sadly, I have also been involved in rescuing several FPGA designs that have gone badly astray. As I worked on these problem designs, it became apparent that -- although the target applications and the members of the development teams were different -- the designs shared some common points that doomed them to failure before the first engineer even sat down to write the first line of HDL code.
With this in mind, I thought I would run through five common issues that I've observed as part of rescuing these projects. These issues are as follows:
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