These days, equipment makers that lack large line-card engineering teams function somewhat like systems integrators. Rather than designing a line card from the ground up with subscriber-line interface circuits (SLICs), codecs and relays, they rely on evaluation platforms, reference designs, software development kits and field application engineering teams provided by communication IC suppliers.
As a result, many IC suppliers are morphing into subsystem-level suppliers for system integrators. Successful chip companies must therefore master integration at multiple levels-from IC to board to system. Moreover, integration schemes for communications infrastructure are being driven by one overriding factor: cost reduction.
In this bearish market, there must be a substantial cost benefit in doubling the line density of a device or a line card, or in adding new on-chip functions. Integration for integration's sake is a recipe for failure in today's highly competitive communications market. Sensible integration schemes that reduce capital expenditure and operating expenses and extend the life of existing equipment will be embraced by today's increasingly cost-conscious carriers.
The modern codec consists of analog-to-digital and digital-to-analog converters for the voice paths and various digital signal processing functions, such as digital filtering, impedance synthesis, balance filters, and programmable gain and attenuation. Those functions are typically realized in CMOS technology.
Packing as many lines as possible onto the same die is an effective way of reducing the per-line cost of a line card. Four-channel devices have become commonplace in the industry. Octal codec devices are also available, with 16-channel codecs looming on the horizon.
It is even possible to design a 32-channel codec, but would it be practical? Probably not in today's market. If such a part were to fail in a central-office line-card applicat ion, it would bring down 32 voice lines at once.
There are numerous variables to consider when designing multichannel codec devices for analog line cards. Many of today's low-to-medium-speed mixed-signal CMOS devices are fabricated on 0.35- to 0.5-micron process technology. As in many CMOS applications, one consideration for increasing density would be to use even finer-line CMOS line geometries, such as 0.25-, 0.18- or even 0.13-micron technology. This makes a lot of sense for high-speed devices with high levels of functionality, such as PC or network processors, but one should be careful before applying deep-submicron technology to today's voice codec applications.
On any CMOS design, there are three aspects of a process technology shrink. The first is the digital portion of a chip. Generally, the area consumed by this circuitry will shrink proportionally to the area shrink provided by the technology. The second aspect to consider is the analog portion of the chip. Analog circuitry does in deed shrink with the process technology, but not nearly as much as digital circuitry. Finally, one must consider I/O pads. The size of an I/O pad is determined by the device-packaging capability, not the CMOS process technology.
Other techniques are available to reduce the cost of the codec function. One possibility is to separate the analog function of the codec onto a separate chip and build it in an older, more stable process technology, such as 0.35 or 0.5 micron. A number of analog codec channels may be built on the same chip, but since there is very little analog circuitry that can be shared, there are limits to how much additional cost reduction may be realized with that technique.
With the digital functionality of the codec, however, deep-submicron technologies yield speed and die area savings. Higher-speed technology means that digital circuitry can be shared across multiple codec channels. The only limits are the process technology speed limits and the architecture chosen to implement the DSP functions.
Just as codec line count and functionality can be enhanced through integration, analog designers look for ways to increase the density and performance of SLICs. Typically paired with codecs on analog line cards, SLICs were originally composed of hybrid circuits on ceramic substrates. That approach gave way to single-channel solid-state SLICs produced in high-voltage bipolar processes (either junction isolated or dielectrically isolated).
Single-channel SLICs are now being challenged by dual-channel SLICs that capitalize on improvements in both analog architectures and packaging technology to reduce the cost and increase the density of high-line-count central-office line cards.
Integrating two SLICs on a single die may sound straightforward, but it is actually a significant engineering challenge. In developing such a high-voltage dual-channel device, the IC d esigner must take into consideration such effects as signal crosstalk and thermal management. With significant crosstalk, undesirable effects can range from the obvious, such as a caller on one line hearing a conversation on another line, to more obscure effects, such as false ring trips. Proper thermal design will ensure that in case of a fault, only the line with the fault will be affected, and not the second line served by the other SLIC sharing the package.
With the challenge of designing a dual SLIC now mastered, what about taking SLIC integration to the next level? Creating a quad SLIC is probably beyond any conventional packaging capability. With four high-voltage channels packed onto a single die, the technical issues increase exponentially. Substrate and circuit crosstalk become monumental problems, not to mention power-management and heat-dissipation issues.
Bright analog engineers might be able to overcome those challenges, just as they might succeed in designing a 32-channel code c, but at what cost? This example shows that there are logical limits to integration, and that unrestrained integration can be counterproductive to saving costs.
Analog line cards prevalent in central-office and digital loop carrier equipment represent an application in which the economies of scale readily apply. With 16-channel line cards becoming old technology, it is not uncommon for communication equipment suppliers to consider 32, 48 or even 64 line counts per card.
A typical line card contains voice codecs, SLICs, relays for ringing and testing, protection circuitry, ringing circuitry and an ASIC, which concentrates the PCM buses into what is usually a proprietary backplane bus determined by each service provider.
How can line-card manufacturers increase line counts in a straightforward, cost-effective manner? One obvious approach is to use multichannel codecs and SLICs. Another method of increasing line density on an analog line card is to use solid-state relays, such as line- card access switch (LCAS) devices, which have all but replaced bulky electromechanical relays. The combination of dual SLICs, quad codecs and small-footprint LCAS ICs has resulted in enormous gains in line-card space efficiency.
An important consideration in reducing the cost of switching systems is whether the increased number of lines squeezed into a typical analog line card is within the limits of the equipment maker's ability to rework board layouts, achieve test access and maintain high reliability with the increased thermal load placed on the system. At the line-card level, it becomes quickly apparent that the key to further cost reduction and enhanced functionality must be realized through functional integration.
Variety of technologies
In the early days of the digital telecommunications infrastructure, only a few component suppliers had more than one technology available to support the line-card market. For example, an IC supplier might be able to provide a CMOS voice cod ec but not a bipolar SLIC, or vice versa. Other suppliers provided secondary protection devices, while still others provided specialized electromechanical relays tailored to the needs of the telecom market.
As a result, the typical line card became compartmentalized by discrete functions. A line card had discrete codecs, SLICs, relays, protection, backplane interface ICs and so on. Each of those devices generally was produced by a different supplier and was not designed to optimize functionality in the interface to the other line-card components. Because of those unique areas of specialization, the system designer spent time integrating related functions and using valuable board space to accommodate necessary discrete interface components.
As the number of channels per device has increased, the functional barriers dividing the devices has eroded. The SLIC/codec chip set has demonstrated the benefits of uniting those two capabilities to enhance line-card density and functionality.
Re cent advances in packaging technology pioneered by Agere's Voice Interface Solutions-now a division of Legerity-have encouraged the economical integration of SLIC and LCAS devices within the same package. SLICs with integrated solid-state relays have been introduced in highly cost- and space-sensitive markets to capitalize on the synergy between the high-voltage lineinterface and relay functions.
Examples of the impact of system integration on line-card designs extend well beyond traditional line-card functions. The latest families of SLIC/codec chip sets are now capable of analyzing the local loop to test and identify changes in the local-loop characteristics. This information can then be used by the system administrator to target additional tests, dispatch a truck roll or even dynamically adjust the line-card performance to compensate for changes in loop characteristics. SLIC/codec chip sets with integrated loop-testing capability can thus reduce the traditional test head requirements, as well as maintenance time and operating costs.
The power of a DSP-based voice codec/filter can even be used to replace traditional "bed-of-nails" manufacturing testing. The codec can perform circuit tests on the line card with a PC connected to the backplane interface on the line card. This methodology can yield significant savings in testing and troubleshooting expenses.
The enormous potential for integration at the board level has long been stymied by the requirement that suppliers must support a wide range of analog/mixed-signal technologies, processes and design skills.
Recently, a few IC suppliers have emerged that can support telecom design and process capabilities in linear CMOS and digital CMOS as well as high-voltage bipolar. This has resulted in the benefits of digital MOS skills being applied to traditional linear MOS design issues. High-voltage technologies used for SLICs are now used to design solid-state relays, secondary protection and even line driver s for such applications as asymmetric digital subscriber lines.