Wireless-infrastructure designers today must deploy complex 3G networks even as service providers demand lower system costs. A key element of the communications network, the radio basestation, requires diverse components fabricated on a wide variety of processes. Ideally, 2.5/3G basestations will support flexible, multicarrier transmission, offering operators added capacity and low-cost service upgrades. Therefore, basestation designers need IC manufacturers to enable new architectures at reasonable costs.
The challenge is that many of the basestation components are difficult or impractical to integrate. With equipment designers wondering what is the best way forward, the answer may lie in the concept of "smart partitioning." New components using this concept are now designed for IF-sampling receivers, direct RF transmitters, analog/digital predistorter blocks and flexible digital signal processor (DSP) clusters.
Manufacturers are now building antennas, for example, with both diversity, or more than one view of the signal, and directional capability-aiming the basestation capacity where you need it-to improve frequency reuse and call quality.
Most of the silicon action near the antenna and within the transmitter is in power amplifier linearization. A chain of detectors, mixers, data converters and even DSPs is required to quickly digitize and process the power amplifier's output.
The idea is to continuously monitor the multicarrier power amplifier (MCPA) output for drift, power variation, signal quality and spectral emission. DSP algorithms then predistort the input signal with a compensating transfer function such that the overall transmitter remains linear. Inside such a loop, the RF power transistors can be biased in the more-desirable Class AB operating region, resulting in increased efficiency and reliability.
Complementary bipolar processes lend themselves to integration of detectors, mixers and amplifi ers. CMOS and BiCMOS processes can combine high-performance data converters with fast digital processing.
A 3G radio transceiver, meanwhile, includes at least two receive (RX) paths and two transmit (TX) paths to accommodate receive and transmit diversity. For simplicity, a transceiver drawing will show only a single RX and single TX path. But in practice, multiple transmitter and receiver paths are required for multicarrier modulation and decoding. Also, both the receiver and the transmitter require a synthesizer to select the desired RF channel.
If the basestation is a 2.5G, GSM/Edge model, the synthesizers must have high purity and very fast settling. However, for a multicarrier, 3G, wideband code-division multiple-access transceiver, the analog synthesizer becomes easier to build, and additional channel selection may be done in the digital domain (with digital transmit signal processors, or TSPs, and receive-signal processors).
Analyzing the RX chain, the components used are low -noise amplifiers (LNAs), analog filters, RF mixers, RF/IF gain blocks and amplifiers, driving analog-to-digital converters (A/Ds). To build a multicarrier receiver, two key specifications apply: noise figure and third-order intermodulation (IP3). Closer to the antenna, where the signals are smaller, the noise figure is more important to prevent small signals from being buried in noise. But as the signal moves closer to the A/D and is sufficiently amplified, IP3 gains in importance.
Processes such as gallium arsenide are very good for low-noise devices but are not sufficient for high-density functions such as A/D converters. Conversely, CMOS is an excellent process for data converters but provides poor noise performance.
Rather than try to bring all performance requirements onto one piece of silicon, a smart-partitioning approach can be used to maximize integration along performance, cost and power lines, rather than pure analog and digital boundaries. The receiver chain contains some functi ons that have been successfully integrated, including RF LNAs and mixers, and digital VGAs and A/Ds. (Design note: Although it looks good at first glance, integrating the first and second IF stages into a single die fabricated in GaAs has problems. Specifically, at frequencies of 1 and 2 GHz, insufficient isolation on-chip exists to keep RF leakage out of the IF, and to keep the IF signal out of the RF input.)
Analyzing the transmit chain, the components used are digital TSPs, digital-to-analog converters, analog I and Q modulators, filters, variable-gain amplifiers, detectors and preamplifier stages.
Thanks to improved RF modulators, 3G transmitters will likely achieve multicarrier performance using a direct RF upconversion architecture. Traditional problems associated with this architecture can be overcome with the digital compensation that is part of the MCPA adaptive process described earlier. Any residual image that cannot be fully compensated will produce adjacent-channel interference b ut not necessarily degrade the basestation's out-of-band spectral emissions. Although these problems can be overcome, all of the IC components in the transmit signal path (as well as the predistortion measurement path) must exhibit higher dynamic range than older, more discrete TX architectures.
Applying smart partitioning to the transmitter, the digital predistortion algorithms (often proprietary to a specific OEM) will exceed the processing capabilities of programmable DSPs, and thus must be implemented in the most advanced fine-geometry CMOS processes as an ASIC or field-programmable gate array. The mixed-signal components (high-performance D/As) must be designed on a larger-geometry CMOS or BiCMOS process capable of sustaining the dynamic range and bandwidth requirements while possibly providing some additional digital functionality. Finally, smart partitioning suggests that the RF modulator and TX VGA are likely candidates for integration. A balance can then be struck between an optimized mixed- signal chip and a highly integrated RF chip.
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