Benefits, risks in 90-nm SoC solutions
By Jeffrey L. Timbs, Director of Systems and Architecture, Larry Wakeman, Development Manager, Agere Systems, Allentown, Pa, EE Times
October 20, 2002 (1:03 p.m. EST)
With the availability of 90-nanometer process technology, system architects certainly have a new capability for optimized system-on-chip (SoC) solutions. However, depending upon proven capabilities with SoC designs, the cost/benefit of optimization options must be carefully weighed against assumptions on technology maturity. In today's environment, the best approach forces the designer to consider the requirements of the entire subsystem rather than those of only a single component.
Looking toward "all-Internet Protocol" transport requirements, many mobile-system vendors want to retain ATM transport capabilities supplemented by IP transport options. Typically, low-speed wide-area network links (T1/E1) will continue to be used because of their ubiquity and the continued unavailability of affordable higher-speed links. But the combination of low-speed data links and increased protocol overhead of IP protocols for speech or low-speed data requires additional functions for optimized link use with low latency, such as header compression techniques. Likewise, use of low-speed data links to transport high-speed data flows requires the use of link-bundling techniques such as inverse multiplexing over ATM or Multi-Link Point-to-Point Protocol (ML-PPP). Finally, the forward-link data path requires intra-Node-B IP forwarding support ,while the reverse-link data path requires IP traffic management support. Together, these additional functions increase the basic feature set for the radio basestation transport subsystem.
OEMs have two fundamental design alternatives when designing next-generation communications systems: SoC integration or a programmable solution built around a general-purpose processor.
An SoC integration strategy promises a long-term cost advantage while offering feature-rich solutions within aggressive cost and power consumption constraints. But SoC strategies represent significant design challenges and in the short term can represent cost hurdles-a common dilemma when choosing a cutting-edge technology. Some silicon vendors skirt the problem by redefining the solution in a narrow sense and then offer the customer semiconductors that address the limited goal, leaving the OEM to fill in the gaps.
A second design alternative is to compensate for lack of functional coverage by opting for a programmable solution based on a general-purpose processor. But this approach does not address the cus-
tomer's need for a complete solution that optimizes functionality against total cost, where the cost calculation includes power consumption, area used and total development time.
In general, OEMs and system designers benefit from solutions that solve more of their problem without sacrificing architectural flexibility. The key for the silicon designer is to avoid leaving a large homework problem for the customer-something that can be addressed by simplifying the SoC application programming interface (API).
The r isks associated with SoC integration must be mitigated by a strong hardware/software co-development effort. The ability to get an early look at operations, administration, maintenance and provisioning for SoC/subsystem solutions improves the accuracy of system turn-up and reduces overall design cycle times, enabling some customers to be operational within an hour of installing new devices.
Co-development environments are essential to bridge the gap between design intent and device samples by providing the capability for system software developers to configure, debug, simulate and integrate software for an entire networking-subsystem solution. Codevelopment platforms promote rich APIs as well as efficient integration and analysis, speeding time-to-market.
The complexity of today's ATM and IP architectures and network economics is being addressed by the capabilities of new silicon, taking advantage of shrinking geometries and new co-design approaches. For example, ATM equipment OEMs can take advantage of real SoC devices designed to accommodate today's ATM-based Node-B transport interface requirements. These devices now integrate an eight-port full-function T1/E1/J1 framer, inverse multiplexing over ATM (IMA) and a user-to-network-interface transmission convergence sublayer, as well as a full ATM traffic management layer and packet adaptation functions for ATM adaptation layers 2 and 5 (AAL2 and AAL5). An embedded ARM960 is also onboard, for management layer processing.
One such device available today consists of 130 million transistors (approximately 4.5-Mbit/second logic gates and 13.5 Mbits/s of embedded SRAM) and was produced in 0.16-micron technology, combining functions from several standalone devices of an earlier generation. The SoC device realizes a reduction in footprint, power and cost for system designers while at the same time enabling packetized voice and data transport over a selection of transport techniques.
Compared with 0.16-micron technology, however, 90-nm d esigns may consist of up to 20 million gates through integration of several chip-level macroblocks. A macroblock is a communication intellectual-property function that may be provided as a standalone chip in prior process technology. Readying chip-level products for integration as subchip macroblocks requires careful partitioning and reusability guidelines.
A methodology that enables process migration of intellectual property and uses formal techniques for functional verification is essential to large SoC designs. Reuse methodology at 90 nm requires the team to rely more on logic built-in-self-test, on-chip ad hoc self-testability and timing closure, simply because automated test equipment cannot test 20 million gates with acceptable coverage. Market cycles mandate fully functional devices without the luxury of time for bottom-up reverification of macroblocks.
Another consideration in moving designs built in prior process technologies forward for integration involves the effects of routing parasitics and crosstalk, which impact timing closure of the new 90-nm design. To make all this happen in a world of shrinking geometry and more devices per square centimeter, IC designers will need to take advantage of signal-integrity analysis and flip-chip IC/packaging co-design tools from commercial CAE tool vendors. These investments enable ASIC customers to reuse the same communication intellectual-property macroblock functions and tools created and tested by the silicon vendor, typically as part of either an ASIC or application-specific service processor product development.
Flip-chip packaging co-design tools provide a seamless link between package substrate design and silicon floor planning, placement and routing that becomes important as packages evolve from 1,900 to 2,500 balls. The tool allows you to define legal bump locations and to keep out regions for memories, phase-locked loops and so on, and also makes it possible to mix serdes macros with area array cells while specifying signal a nd power/ ground bumps.
User-configurable, embedded SRAM with self-repair and customized asynchronous multiport memories enables optimal performance and area. Crosstalk mitigation benefits arise from Web-based signal-integrity analysis tools and layout-oriented "correct-by-construction" approaches related to gate sizing, route spacing and buffer insertion. The signal-integrity analysis tools typically analyze more than 500 blocks or chips per month.
Turning back to the additional features required for all-IP mobile-transport subsystem solutions, by extrapolation from 0.16 micron, it's clear that 90 nm certainly enables a solution with a 4x improvement in raw gate density and at least a 2x improvement in speed. Memory cell size improves by 2.5x, while dynamic power is 0.09x that of the 0.16-micron process. As a result, embedded memory, which makes up a substantial portion of a packet/cell transport solution, can scale even further to satisfy the additional processing steps introduced by IP tra nsport, such as incorporation of various header compression algorithms as well as rich IP forwarding and classification rules.
Moreover, the incorporation of on-chip Layer 2 processing (link/bundle management and framing per IMA and ML-PPP) and packetized-voice multiplexing/demultiplexing (AAL2 or IP/UDP/RTP flows) makes up the entire data path of an all-IP transport solution while retaining ATM transport alternatives.
While technology provides the opportunity for system-level solutions and benefits, the economics of the development process will continue to pressure the SoC design cycle. The ability to provide meaningful solutions to system-level problems requires a broad intellectual-property and analysis portfolio.
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