Achieving FPGA Design Performance Quickly
Joe Mallett, Synopsys
EETimes (2/8/2017 11:20 AM EST)
This column highlights the broad steps designers need to complete as they close timing and how tool automation helps to simplify the process.
Today's engineering teams are tasked with delivering FPGA-based products under incredible schedule constraints to market windows. Closing timing constraints is still a challenge for many designers. FPGA design tools are a necessity to help define and apply the correct constraints to a design to quickly close timing and complete the project. This blog highlights the broad steps designers need to complete as they close timing and how tool automation helps to simplify the process.
- Design setup
- Initial timing constraint setup
- Constraints tuning
When starting a new project, designers need to setup the environment and import the IP for the design, which may come from multiple sources. FPGA design tools help automate this process for designers, making it easier and faster while also helping to remove import errors from the process. In addition to the IP import, the tools should automate the constraint import for a given block. These constraints will be shown in the FPGA Design Constraints (FDC) files within the tools, showing the correct syntax for things like clocks, I/O, and clock groups.
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