We in the technology sector woke up after the euphoric party of the high-tech boom with a ringing hangover, only to learn once again that clichés are born in fact and that what goes up inevitably must come down. As the hangover has waned, we have started to reevaluate what we do and how we do it. The most obvious result of this reevaluation has been layoffs and company closures. The not-so-obvious effect, however, has been the reevaluation of technology and product-delivery value propositions.
Innovative technology is no longer the driver it once was. Like the flight to safety in the stock market, companies engaging in chip design have also sought shelter in doing what they do best. The mantra today is "low risk" or, better still, "no risk."
That has caused a dramatic shift in expectations and product offerings from companies up and down the ASIC or custom-logic design value chain. The once-attractive distributed model of putting a chip toget her (customer-owned tooling, or COT) has lost its luster and is being replaced by tightly coupled and integrated models where risk can be controlled. The challenge will be providing an acceptable risk option, with product execution assurances at reasonable cost, and providing innovation in an industry where specialization and outsourcing have become commonplace.
ASICs have replaced discrete memories as the main process technology driver in the industry, outside of the tightly controlled environment of microprocessors. Design requirements for high-end systems-on-chip stretch the capability of commercially available EDA tools beyond their limits, particularly in the areas of verification, test and avoidance of deep-submicron effects. Hence, the design productivity gap (the gap between the capabilities of the process technology and the EDA tools) continues to widen.
Yet process technology is not the main driver in terms of product differentiation. Design tools and methodology are very important consid erations. Today, markets drive technology. Predictable time-to-market is key, and product life cycles are short. The mantra now is "right first time and on time."
Today's ASICs in the communications and storage markets use 0.13-micron technology. They often include 5 million to 10 million logic gates, with multimegabits of embedded memories; high-speed I/Os, to 6 Gbits/second; and predefined intellectual-property (IP) blocks, or cores-all of which can be running at 250 MHz or higher. Design programs today can cost up to $10 million. Projects now require a great deal of specialization and automation in the design process.
The move from COT at the 0.13-micron node shows that customers want to engage with an ASIC provider to reduce risk. At the same time, an ASIC provider cannot and should not develop the entire ASIC capability in-house. It must use what's best in the industry along with internally developed elements, and then incorporate those items into the ASIC product. All externally sourced deliv erables must work the first time, since the cost of a redesign is high not just in absolute numbers but also to the customer that misses a market window.
These time-to-market and overhead forces are now causing a new breed of ASIC suppliers to emerge from the traditional integrated-device manufacturer. The new supplier's value-add is to use design elements or tools developed internally or externally, integrate them into a robust design system and deliver what is ultimately important to the customer: right-first-time, on-time and working silicon. The days of having to develop and deliver all the requisite technology to a customer, while meeting the customer's time-to-market needs, no longer exist.
It is the nimble and adaptable ASIC supplier that will reap the benefits of a growing ASIC market where customers can still take advantage of performance, IP, logic differentiation and a cost-effective silicon platform.
Ronnie Vasishta is Vice President of ASIC Technology Marketing for LSI Log ic Corp. (Milpitas, Calif.).