Dynamic Margining: The Minima Approach to Near-threshold Design

By Minima Processor

Executive Summary

Energy consumption has become the most important parameter for today’s batterypowered electronic devices. The need to reduce energy consumption has led the industry to reconsider the concept of near-threshold design. Legacy design, a static margining approach to power/performance trade-offs, will leave most of the potential energy savings on the table. New offerings in this arena include both integrated circuit (IC)-based and intellectual property (IP)-based solutions, where IP-based solutions offer a faster time-to-market among other benefits.

The Minima dynamic-margining approach adds both hardware and software IP to customer-specified standard components (such as the Arm Cortex-M3 processor) to enable the device to function at its lowest possible power for any given task, data, or ambient condition. In addition, the Minima solution includes an ultra-wide dynamic voltage and frequency (DVFS) implementation that realizes far more energy savings than standard DVFS implementations using only 2-3 set states. Together, these technologies enable energy savings of 15-20x over nominal-voltage operation.

Near-threshold Power: An Old Idea With New Momentum

For decades, performance has been the key parameter for electronic designs. However, battery-operated devices are now the most ubiquitous electronic devices; the growth of the internet of things (IoT) will only increase the importance of battery-life control and today, energy is the driving design parameter. Performance is still very important, but now it must be balanced against the need to prolong battery life.

As low-power design has become an important consideration, the industry has deployed many approaches, both new and not-so-new. One newer approach is energy harvesting, the process by which energy is derived from external sources (e.g. solar or light energy, thermal energy, and kinetic energy) and stored for use in electronic devices. This approach has promise, but is challenging, because it is hard to build very small energy harvesters, and a large form-factor is inherently at odds with the small scale of battery-powered devices.

Another, not-so-new approach is sub-threshold and near-threshold voltage design. The energy consumption of a transistor is quadratically related to its operating voltage, so lowering that voltage is the most straightforward way to minimize energy consumption. The concept of sub-threshold design has been around since the 1970s. The threshold voltage is the voltage at which a transistor turns off. It is well known, however, that in practice, a transistor will function well below this nominal threshold. Sub-threshold design operates transistors using leakage current – with the transistors in the “off” state – for low-power applications. Near-threshold design operates transistors at or near their threshold (but still well below their nominal operating voltage), but they are still “on.” The near-threshold approach mitigates the difficulties of sub-threshold design, but keeps most of the benefits.

Sub- and near-threshold design is challenging due to two main factors: the standard characterization of transistor and cell models, and a large dependence on process and environmental variation. Standard transistor and cell models are only characterized at well above threshold voltage, so their performance below these levels is undocumented. Using traditional design methods to accelerate this process – adding margin – would quickly erode any benefit.

Process variation and environmental operating conditions both have a large impact on performance parameters in any given transistor or cell. When transistors operate outside their normal nominal operating region (i.e., sub- or near-threshold), their susceptibility to parameter change increases greatly, both from transistor to transistor and across the design. Although gates function well below threshold voltage, this susceptibility leads to performance parameters varying wildly at low voltage (Figure 1).

Figure 1. Process variation for transistor function at and below threshold levels. The performance at near-threshold voltages is subject to some variation; however, at subthreshold voltages, performance varies wildly. (Key: TT= Typical, FF= Fast, SS= Slow)

This creates a situation where either yield goes down considerably (unacceptable), or again, benefit-robbing margins are added. Environmental operating conditions (e.g., heat, humidity, aging) add their influence to this mix: transistors that function near-threshold at 21 degrees C may not function at 49 degrees, yet a device left inside a closed car could easily reach this temperature.

Mainstream design shied away from sub-threshold voltage because these voltage levels, applied with static margins, resulted in unacceptable performance and little power savings. Other than a handful of applications, such as pacemakers and RFID tags, sub-threshold power design hasn’t been adopted for broad commercial applications.

However, with energy savings being such a strong focus today, the industry has reawakened to the possibilities of near-threshold power design, and several solutions have emerged that seek to overcome the obstacles of slow, time-consuming development and process/environmental variation.

Today’s Near-threshold Solutions: Seeking the Practical Solution Space

Today, there is general agreement that the goal is to create a practical solution space, where significant energy savings are realized, without sacrificing too much performance, or too much development time and while maintaining required yield. The solutions offered today are delivered either via fabricated microcontrollers (ICbased), or IP-based solutions.

For the fabricated products, the path-to-market is conventional: OEM designers integrate these low-power microcontrollers into their consumer products. Because these are manufactured devices, however, their time-to-market is long compared to the IP-based solutions. Adding to the long time-to-market is the fact that fabricated microcontrollers are designed with specialized cell libraries that have been fully and carefully recreated for sub- or near-threshold operation. Creating new cell libraries for sub- and near-threshold voltages is extremely laborious and slow. This arduous step also must be repeated for every new semiconductor process. In addition, the repercussions of a bug in this kind of device, as for any manufactured IC, can be very large.

IP-based solutions license the low-voltage design to SoC integrators that build microcontrollers or other ICs. This approach is more nimble, and enables faster time-to-market, a larger application library, and fast turnaround for bug fixes. But a conventional IP-based approach would still require the creation of specialized libraries; these would have to be distributed along with the low-power design IP.

The biggest problem with all these offerings has been a static approach to margining: they find the worst-case intersection of both power and performance and then design the device or IP to keep power above this level. This is like having a highway with mostly straight, flat, multi-lane sections, but also a few single-lane, curvy, mountainous sections, and setting the speed limit for the entire highway to be safe for the most acute driving conditions. It is effective in preventing a crash, but very inefficient in terms of moving traffic. Static approaches, whether implemented in devices or as IP, simply leave a lot of the potential benefit (both in terms of lower power and higher performance) on the table.

Minima Margining: Margining for Near-threshold Design

Minima uses an IP delivery model that adds both hardware and software to CPU and DSP processors. The essential difference in the Minima approach is dynamic margining for power. Minima IP enables the device to modify power usage during operation in response to performance needs, process variations, or environmental conditions in real time. Unlike static approaches that seek to make a gate library very robust for low-power operation, the Minima dynamic-margining approach makes sure the operating conditions are correct in real time. This approach enables Minima to take any existing processor and DSP architectures into the microwatt range (Figure 2). This also allows Minima to use the “vanilla” gate libraries that are only re-characterized for low voltage – an extremely lighter process than a full library makeover.

Figure 2. Minima can take any existing processor and DSP architectures into the microwatt range.

Minima uses a path-based implementation, adding timing monitors along paths to monitor power and performance during operation (Figure 3). If a critical path monitor is activated by a voltage droop, whether due to process variation, temperature conditions, or aging, Minima software optimization and dynamic feedback enables a response to temporarily slow the path for a clock cycle, or until conditions allow a resumption. In this way, the OS-controlled Minima middleware acts like an automatic braking system that adjusts to driving conditions. Instead of driving all operations on worst-case assumptions, Minima tunes for bestcase/ nominal operation, and slows operation when necessary – but only for as long as necessary. This means that the circuit can function at its lowest possible power for any given task, data, or ambient condition.

Lowering operating voltage through the Minima margining approach delivers substantial energy consumption savings, without excessive impact on performance, and while maintaining yield. The average energy savings is 15-20X over nominalvoltage operation when using Minima margining combined with ultra-wide DVFS.

Figure 3. Minima adds timing monitors along paths to monitor power and performance during operation.

Maximizing Savings: Minima Ultra-Wide DVFS

Minima middleware includes DVFS to enable low-power operations to take place at the lowest possible voltage. DVFS is not a new concept; it has been used in highend processors since the early 2000s, and later in high-end mobile application processors. However, DVFS implementation in microcontrollers still is very limited with only 2-3 set states that are determined during the design phase.

Minima employs an ultra-wide DVFS implementation in its middleware to enable circuits to execute always-on, low-performance tasks (display housekeeping, speech vs. noise detection, etc.) at the lowest voltage possible while maintaining the possibility to ramp up to the requirements of high-performance tasks almost immediately. Today, microcontrollers with DVFS operate in a fairly tight range around the nominal 1V power (0.9-1.2V), and so don’t realize great energy savings from this strategy (Figure 4). High-end servers may use DVFS for some functions down to 0.6V. Minima ultra-wide DVFS enables applications such as Bluetooth and IoT devices that have a “listening mode” (e.g., home-control speaker units) to maintain their various housekeeping modes at much lower levels (0.35-0.7V). This enables DVFS to afford significant energy savings.

Figure 4. Minima technology dynamically adjusts the processor’s operating voltage and performance. For example, when dropping from high performance (e.g. 64MHz@0.7V) towards a lower performance point (e.g. 2MHz@0.35V), the Minima HW-SW interface signals that this performance point cannot be reached and this processor’s actual Minimum Energy Point is 2MHz@0.4V. Adjusting happens both during DVFS changes and at a single performance state. Dynamic margining also improves yield, especially at low voltages.

Minima and the Arm Cortex-M3 processor

Customers engaging with Minima choose the processor core that suits their needs, and Minima adds the hardware and software IP to enable dynamic margining and ultra-wide DVFS.

As an example, Minima offers a solution for the popular Arm Cortex-M3 processor – currently being used in billions of chips and easily licensed for no upfront fee, just a success-based royalty, through Arm DesignStart. The Arm Cortex-M3 is a natural fit for duty-cycled, low-power design due to its many low power and sleep features. Minima technology enables the ultra-low energy levels required for always-on applications in addition to the many existing features:

• Two architectural sleep modes: normal sleep and deep sleep. The sleep modes can be further extended with vendor-specific speed control features. Within the processor, both sleep modes behave similarly.
• Two instructions for entering sleep modes: WFE and WFI. Both can be used with normal sleep and deep sleep modes.
• Sleep-On-Exit (from exception) feature: allowing interrupt driven applications to stay in sleep mode as often as possible. When enabled, the processor enters sleep automatically when finishing an exception handler and if no other exception is pending. This reduces power by avoiding extra active cycles of executing code in Thread mode, and reduces unnecessary stack operations.
• Optional Wake-up Interrupt Controller (WIC): this optional feature allows the clocks of the processor to be completely turned off during sleeps. When this feature is used with state retention technology, found in certain modern silicon implementation processes, the processor can enter a powerdown state with extremely low-leakage power, and it is still able to wake up and resume operations almost immediately.
• Clock gating and architectural clock gating: Allows clocks for registers or sub-modules of the processor to be turned off to reduce power.

In addition, various characteristics of the Cortex-M processors also help to reduce power consumption:

• High performance: The Cortex-M3 processor with 32-bit performance allows the same computational tasks to be carried out in shorter time and the microcontroller to stay in sleep modes for longer periods of time. Alternately, the microcontroller can run at a slower clock frequency to perform the same required task to reduce power.
• High-code density: By having a very efficient instruction set, the program size can be reduced hence requiring a smaller size flash memory to further reduce power consumption and cost.

The Low-Power Future

Energy consumption is the greatest area of pressure for electronic devices today, and will only become more critical in the coming years as the IoT expands. This intense focus on low-power design has brought the once-sidelined idea of nearthreshold voltage design back into the spotlight.

Minima margining is a unique IP approach to near-threshold voltage design that combines hardware and software to provide dynamic margining for near-threshold voltage design. Minima uses an ultra-wide implementation of DVFS in its middleware to enable the lowest power operation with a best-case/nominal operation target vs. the worst-case target used by static approaches. The average energy savings realized through the combination of dynamic margining and ultrawide DVFS is 15-20X over nominal-voltage operation.

Get started quickly and reduce time to market by accessing the industry-leading Arm Cortex-M3 processor and its verified subsystem, for no upfront license fee, through Arm DesignStart – designstart.arm.com. Take advantage of the wealth of tools, support, training, and ecosystem partners to make your silicon a success with Arm.

Access the Arm Cortex-M3 processor for free

If you wish to download a copy of this white paper, click here