by Rick Mosher, AMI Semiconductor, Plano, Texas
Current communication systems utilize highly complex SoC designs for numerous applications. Hardware designers must overcome many complex and challenging issues regarding cost, time-to-market, capacity, performance, power, quality and IP. This paper compares three approaches to implementing SoC designs: FPGA design to production, ASIC design to production and designs targeted for FPGA to ASIC translation. The latter approach is the focus of this paper.
FPGA TO ASIC STRATEGY FOR COMMUNICATION SOC DESIGNS
While communication systems are getting more complex, market windows are getting smaller and resources are shrinking, especially in today's regressed market. Most of these systems utilize highly complex SoC designs. There are many complex and challenging issues the hardware designer must overcome when developing a system on a chip.
Two of the primary issues all hardware designers and hardware design companies must overcome is cost and time-to-market (TTM). Increasingly, more and more pressure is being asserted to do more with less (less money, less people and less time). In today's economy, where customers are buying fewer products, a supplier must increase the number of customers they do business with to stay profitable. If a supplier finds a market niche to exploit, they need to get their product to market before their competition; otherwise they cannot increase their customer base. This paper will take a close look at the cost and TTM issues and recommend methodologies to help with both when designing a SoC.
Capacity is another key issue when discussing SoC designs. Modern communication SoC designs usually incorporate a processor or processors, internal block memory, interface blocks to external memory, numerous communication interfaces and peripherals. As such it is easy to see how these designs can grow to multi-million gate designs, relatively easily. This paper will discuss the capacity issue and how it impacts different methodologies.
Performance and power have always been a delicate balance to maintain when designing digital hardware in general and it becomes an even greater issue when designing SoCs. SoCs usually are large designs, greater than a million gates, that contain high-speed processors and data links. As such, SoCs by nature are power hungry. Add to that the power inefficiencies of high-end FPGAs and you have a device that is going to consume a lot of power. This paper will examine power requirements closely and recommend methodologies that can help save power while still maintaining the performance required for the application.
Another big technical issue when dealing with complex designs is quality. The last thing a hardware supply company wants to do is sell faulty equipment to key customers, or any customers for that matter. Therefore, using a design methodology that will ensure the least amount of risk is highly desirable for everyone from the design engineer in the trenches to the CEO. This paper will examine quality issues and recommend methodologies, which have been proven to minimize the risk associated with SoC design.
Intellectual Property (IP) is another issue, which needs to be tackled by the design engineer. The type, amount and quality of the IP used can greatly affect the other issues of cost, TTM and quality. This paper will discuss the different aspects of IP, and how they relate to the three design methodologies: FPGA design to production, ASIC design to production and designs targeted for FPGA to ASIC translation. Designs targeted for FPGA to ASIC translation can help to resolve or minimize the impact of all the design issues noted above, with the exception of TTM. For TTM the FPGA to production methodology wins first place but the FPGA to ASIC translation methodology is a close second. The FPGA to ASIC translation methodology is the focus of this paper.
EXPLORING THE ISSUES OF SOC DESIGN
As mentioned in the overview there are seven primary issues to consider when starting a SoC design: Cost, Time-To-Market (TTM), Capacity, Performance, Power, Quality and IP. This section will define all seven issues. Later in the paper the different methodologies will be discussed as to how and to what degree they impact these issues.
Everybody knows that minimizing cost on any engineering project is important. When people think about FPGAs they immediately think high per unit cost and when they think about ASICs they think high up-front cost or NRE (Non-Recurring Engineering). So which technology offers the most cost effective solution? This question will be answered in the following sections that compare the different design methodologies. Finally, a recommendation will be made on the most cost effective solution.
Time-to-Market or TTM is another very important issue that has to be taken into account when starting a new SoC development project. TTM is not only critical in beating competitors to market but it also impacts the overall cost of the project. The longer it takes getting a product to market the greater the impact to market share. In fact, every month a product is delayed, cost the company a 14% loss in market share. Projects that have longer development spans require additional resources (man-hours, tool licensing, etc.). These additional resources also affect the bottom line. Between the impact to market share and the cost of additional resources, it is easy to understand the importance TTM has to every project.
Capacity is another key issue when talking about SoC design. Current communication SoCs can easily reach into the millions of gates. Size may be the determinate factor when considering whether to implement the SoC as an FPGA or as an ASIC. However, even for large SoC designs it is highly desirable to implement a methodology that includes the shorter FPGA verification cycle. Later in the paper we will discuss a methodology, which will enable FPGA verification cycles, even for multi-million gate designs.
As communication systems evolve, terms like bandwidth and bit-rate take on greater importance. SoC designs within those systems need to squeeze out as much performance as possible to keep up with data rates measured in gigabits per second. Achieving greater performance is always a goal when designing complex SoC used in communication systems.
Power is another critical resource in today's communication systems. As handheld wireless devices get smaller and smaller the available power decreases while at the same time the complexity of the device increases. All this means that SoC designs used in such devices must conserve as much power as possible. Lower power equates to smaller less expensive power supplies, savings on board space and fewer cooling components, which all help to reduce overall cost.
There are two types of quality, which will be examined: design quality and manufacturing quality. The first quality issue, design quality, refers to whether or not the application functions as specified. The second quality issue, manufacturing quality, refers to the quality and reliability of each manufactured device. Both are critical in providing quality parts to the customer.
Design reuse in the form of proven IP cores can greatly reduce TTM and increase quality for SoC designs. According to Dataquest by 2005 SoCs will contain 80% pre-define IP blocks and 20% custom logic. By 2010 the percentage of IP contained in a SoC is predicted to grow to 95%. This increase in demand for IP cores has lead to an explosion of IP core vendors in the market. The use of IP cores gives designers the flexibility to concentrate most of their time on the application specific material while spending a small amount of time on common design blocks. The final effect is a substantial increase in overall productivity, which leads to a substantial decrease in TTM. Also, once an IP block is mature (has been used in numerous designs) the risk associated with implementing the core is minimal and results in higher design quality.
COMPARING DIFFERENT METHODOLOGIES
Next let us examine the three design methodologies being presented in this paper: designing a SoC into an FPGA and taking the FPGA to production; designing a SoC into an ASIC and taking the ASIC to production; designing the SoC into a FPGA then translating the FPGA into an ASIC and taking the ASIC to production. Each design methodology will be analyzed on how it impacts the seven key issues of cost, TTM, capacity, performance, power, quality and IP.
FPGA to Production
The biggest advantage of designing a SoC to FPGAs for production is the short span from concept to production. Since FPGAs act as their own prototypes, the time needed for each verification iteration is minimized. FPGAs also allow the flexibility of specification changes at anytime during the flow. Of course, serious specification changes could still have a huge impact on schedule but changes can be implemented at any time during the flow without the added cost of silicon re-spins. Now lets look at how implementing the SoC into FPGAs for production impact the seven main issues.
High-end FPGAs have incredibly high per unit cost, which is growing with every new product released. The latest in FPGA SoC technology, FPGAs which contain embedded processors, memory and other IP, can easily cost more than $1000 per unit. It is easy to see that as volumes grow price per unit will have the biggest impact to profit margins. Conversely, designing to FPGAs for production does minimize the other business related issue by allowing the fastest TTM. This is true when comparing apples to apples. If the TTM is analyzed on the same design where one is implemented in a FPGA and the other is implemented directly into an ASIC, then the FPGA implementation will always have the shortest TTM. However, TTM is also very dependent on other factors within the design. For example, the percentage of custom logic versus proven IP will greatly impact the time it takes to get a product to market. So when it comes to the two business issues of cost and TTM, FPGAs negatively impact cost due to thier high per unit price tag but they offer the fastest TTM of the three methodologies.
Modern SoC designs can easily reach multi-million gates in size. Current FPGA technology can handle designs up to about a million gates but anything bigger will have to either be split into multiple FPGAs (no longer a true SoC) or be designed into an ASIC. Using multiple FPGAs to implement a design would cost an exorbitant amount of money for even small production runs. FPGAs and ASICs are comparable when analyzing embedded memory and embedded IP capacity but when it comes to logic, FPGAs only have a small fraction of the capacity that can be found in ASICs.
FPGAs have improved performance significantly over the last few years. In fact, when talking about embedded RAM and processor performance, FPGAs are comparable to ASICs. However, FPGAs only offer about 50% the performance of ASICs when referring to the programmable logic. When it comes to power consumption there is no comparison. FPGAs will always consume more power than comparable ASICs due to the higher interconnect capacitance inherent in FPGAs.
FPGAs do shine when it comes to design quality. Given the ability to fix bugs at any time during the life of the part without manufacturing a new part is one of the biggest advantages FPGAs have over ASICs. This is especially helpful when the product specification is still in flux while designing the device, which is why many companies will implement a partial FPGA production to iron out feature changes and development bugs prior to converting to an ASIC for cost reduction.
Due to the increasing complexity of SoC designs, availability of proven IP is critical in overcoming the TTM issue. As mentioned earlier there has been an influx of third party IP companies to satisfy the growing demand for IP. This influx has really leveled the playing field for FPGAs and ASICs when it comes to IP availability. This is obvious when one considers that a majority of IP cores are developed and offered in RTL format allowing use in either an ASIC or a FPGA. It is true that there are proprietary cores offered by the FPGA vendors that cannot be licensed for ASIC development but at the same time there are numerous hard cores designed specifically for ASIC technology that cannot be utilized in a FPGA. So the total amount of IP available for both FPGA and ASIC design is quickly leveling out and becoming a non-issue when choosing between the two technologies.
FPGA to production methodology offers the greatest flexibility by allowing bug fixes and feature updates through out the life of the part. Another great feature of using this methodology is it offers the fastest TTM. However, the flexibility and fast TTM come a great cost: exorbitant per unit cost; low capacities; large packaging; high power consumption; moderate performance (<200Mhz). FPGA to production methodology is best suited for low volume SoCs where flexibility and TTM are critical issues, while power and performance are not on the critical path.
ASIC to Production
Another methodology often followed for SoC development is to design the application directly into an ASIC for both prototypes and production. The major drawback to doing this is the risk. The only way to prove functionality is through simulations of the RTL source code and netlist. Once in the prototype stage, any errors that need to be fixed or features that need to be added will require a re-spin of the ASIC. Often designers feel that they must follow this flow for designs that are too large to fit into a single FPGA or for designs that have stringent power requirements. The final methodology that is discussed in the next section will demonstrate another option when considering large or power restrictive designs. For now lets take a closer look at how the ASIC to production methodology impacts the seven basic design issues.
When analyzing cost of designing with ASICs, one must consider both per unit cost and NRE. The primary reason ASICs are preferred over FPGAs when considering large-scale production is that the per unit cost of an ASIC is negligible when compared to the per unit cost of a comparable FPGA. But ASICs also incur NRE as an expense. NRE is the amount of money required for engineering services, reticles and tools needed to design custom ASICs. Historically, NRE has limited ASIC design to high volume applications. Today's major ASIC companies have come up with new and innovative technologies, which have helped to overcome the NRE hurdle. Targeting these new ASIC technologies can enable cost effective productions as low as 10k units per year for normal designs and even lower than 5k units per year for complex SoCs. To determine the actual volume where ASIC design becomes cost effective, one just needs to determine the break-even point. The break-even point is when the volume reaches a point where it becomes cost effective to produce ASICs instead of FPGAs. This means that the volume has reached the point where the high per unit cost of the FPGA has overtaken the the total cost of the ASIC (NRE + per unit cost).
Designing directly into an ASIC requires greater development spans, so TTM is always an issue when considering this methodology. Dataquest has stated span times for ASIC development from concept to production of 12 to 18 months. The same source stated that the average FPGA development span, from concept to production, averages six months. The 3X longer development cycle can greatly impact TTM, which can be very costly in the competitive market of communications.
When it comes to performance and power ASICs truly outshine FPGAs. Even though the disparity between ASIC and FPGA performance has diminished over the years it is still substantial as the following chart from Dataquest indicates.
Current ASIC technology offers substantially less power consumption than FPGAs and is unequivocally the best choice for low power applications like cell phones, PDAs and other handheld electronic devices.
ASICs offer SCAN and BIST insertion which greatly reduce undetected manufacturing defects and gives them an advantage over FPGAs when discussing the manufacturing quality issue. Design quality is more challenging for ASICs. The only way to verify functionality when designing directly to an ASIC is through simulations. ASIC prototypes are very expensive and most companies who design ASICs endeavor to avoid re-spins as much as possible. FPGAs on the other hand become their own prototype, enabling lab testing early in the design process.
Dataquest has stated that more than half of current SoC designs consist of proven, pre-defined IP cores. And that percentage is steadily increasing. Do to the increase in demand a majority of standardize functions are already available to ASIC designers as proven IP.
The ASIC to production methodology, while not as flexible as the FPGA to production methodology, offers lower cost, reduced power consumption, greater capacity and faster performance. The downside is the development span required for this methodology and the expensive up-front cost (NRE). The 12 to 18 month span from concept to production is greater than most communication companies TTM requirements will allow and the NRE can easily grow to more than half-a-million dollars for highly complex SoC designs.
FPGA to ASIC TRANSLATION
The FPGA to ASIC translation methodology, shown above, offers many of the pros of the previous two methodologies with few of the cons. This methodology enables the short FPGA type verification cycles while at the same time allowing the cost effectiveness of an ASIC solution during production. Even multi-million gate designs can be prototyped on a board using multiple FPGAs then later translated into a single ASIC. Current software automates the partitioning of a large RTL design in multiple FPGAs. Some ASIC companies also offer software to help automate translating the multiple FPGAs into a single ASIC.
Designing an application into an FPGA through the prototype stage and then translating that design into an ASIC provides the most cost effective solution when designing moderate to high volume applications. The impact from the high per unit cost of FPGAs is marginalized since the FPGAs used in the development will only be used for prototyping. The project still requires a NRE fee when translating to an ASIC but major ASIC companies have designed new and innovative products, which greatly reduce the NRE requirements. Even more money can be saved when either translating multiple FPGAs and standard products into an ASIC for a single product or translating multiple disjoint FPGAs into a single ASIC for use in multiple products. In other words, it is possible, due to greater ASIC capacities, to translate multiple FPGAs that have different functions and belong on different boards into a single ASIC. This requires close coordination on all board designs (same footprint, different IO, etc.) but can lead to enormous cost savings. Translating disjoint FPGAs usually does not apply when discussing SoC applications since, due to their size, they normally require most of the die space on the targeted ASIC. Even discounting disjoint FPGA translation, the miniscule per unit cost of ASICs and the reduced NRE available on new ASIC products easily provides the most cost effective solution when designing all but the lowest volume SoC application.
Development spans in this methodology are a little longer than FPGA development cycles but are significantly shorter than ASIC development cycles. This is true for two reasons. First and foremost, the verification of the device is completed in the FPGA world where the verification cycles are much shorter. Secondly, major ASIC companies offer translation spans that are significantly shorter than standard ASIC spans. The average translation adds 6 to 9 weeks to the overall FPGA development cycle. Even though FPGA to ASIC translation does not offer the best solution for meeting TTM requirements, the cost savings usually justifies the impact to TTM.
Since the end product is an ASIC, designers do not need to worry overly much about the size of their design. If the design out grows a single FPGA, the design can be partitioned into multiple FPGAs for prototyping. Most FPGA vendors offer software that will enable automatic partitioning of the design. This either requires a daughter board or a separate board layout from the production version, but boards are relatively inexpensive in terms of both cost and man power. Once the design is completely verified and the software is fully integrated, the FPGAs are then merged into a single ASIC. Care must be taken when merging multiple FPGAs when it comes to timing, since the interfaces between functional blocks will speed up considerably. As long as good synchronous design practices of registering inputs and outputs from block to block are maintained then reaching timing closure should not be a problem.
Since ASIC technology will be used for production in this methodology, performance and power are not even an issue. ASICs have the edge in both performance and power by a substantial margin. This methodology will work for both low power and high performance applications.
Quality is another key area where this methodology really shines. Using this methodology to design a SoC gives the designer the advantage of designing in FPGAs through the prototype and even limited production for real world system testing. After the design is mature, error free and the features are locked down, the design is translated into an ASIC that is guaranteed to be functionally equivalent. That ASIC is then used for large-scale production runs where the inserted SCAN and BIST help to ensure manufacturing quality.
IP is an issue where the designer, who wants to follow this methodology, needs to be careful. The IP selected for the application needs to be flexible and needs to be supported by both the FPGA and the ASIC vendor. Usually the best solution is to select a third party vendor who licenses a RTL version of the core. There are numerous cores offered by the FPGA vendors which are proprietary to that vendor's technology. However, most ASIC vendors who specialize in FPGA to ASIC translations endeavor to offer IP solutions that are functionally equivalent to the proprietary cores the FPGA vendors offer.
The FPGA to ASIC translation methodology offers the flexibility and efficiency of the FPGA development cycle through the prototype stage; the substantial cost savings of ASIC technology; the greater capacities of the ASIC technology, allowing multiple to one conversions; the low power and high performance of ASIC technology; the quality advantages of both the FPGA technology (design quality) through prototype and the ASIC technology (manufacturing quality) through production. The only downside is a TTM that is not quite optimal. Overall, the pros definitely out-weigh the cons in this methodology flow.
THE ROAD AHEAD
One possibility that is showing up in discussions about where the future is headed in SoC design methodology is the integration of programmable logic into standard cell ASICs. However, there are many pitfalls to over come before such technology will be readily available. Major ASIC companies have already attempted to produce an ASIC with built-in programmable logic but were unsuccessful due to technical problems. Other companies are still trying to produce the golden egg that SoC designers crave: a single product that offers all the field programmability of FPGAs plus all the cost, performance, capacity and power advantages of ASICs. This golden egg may well be unobtainable, but for sure, an optimal solution is still many years down the road.
Another option that is already available from most major ASIC suppliers is the platform ASIC. The platform ASIC contains numerous embedded IP blocks (processors, block RAM, high speed IO, etc.) in a base while offering a programmable array in the upper layers of metal. Notice this programmable logic is not field programmable but it does allow a fast and inexpensive re-spin of the ASIC, which in turn enables design reuse across numerous applications. A few ASIC companies that specialize in FPGA to ASIC translation are designing their platform ASICs to match or surpass the functions being offered by the FPGA vendors. Therefore, designers who want to target platform ASICs for production can still follow the FPGA to ASIC translation methodology.
Throughout this paper three different methodologies have been presented which can be followed when designing SoCs. Even though the last one presented, FPGA to ASIC translation, is the most advantageous, they all have uses depending on design and business requirements. For SoCs that are low volume (below the break-even point), require field programmability or require IP that is only available for FPGAs then the correct choice is to design directly to FPGAs for production. For SoCs that are too big (multi-million gates) to fit into an FPGA and prototyping multiple FPGAs is impractical or when a lack of board space doesn't accommodate the larger FPGA packages, then the correct choice is to design directly into ASICs for production. For all other cases the methodology that will provide the most cost savings, acceptable TTM, greatest capacity, best performance, lowest power and highest quality is to design the SoC using the FPGA to ASIC translation methodology.
| Implementation (Vol > 5k per year) || FPGA SoC || ASIC SoC ||FPGA to ASIC Translation SoC |
| Cost || Too High || Low || Low |
| HW Dev. Schedule (TTM) ||< 0.5 Year || > 1 Year || < 0.75 Year |
|Too high |
|Very Low |
|< 200 MHz |
|> 200 MHz |
|< 200 MHz |
|Die size |
|Very Small |
|Pad limited |
|Risk (Quality) |
|Low risk |
|High risk |
|Moderate risk |
|IP Availability |
 Dataquest; "ASIC Design Times Spiral Out of Control"; Smith, Gary; January 2002
 WindRiver Systems, Inc.; "Current and Emerging Embedded Markets and Opportunities – ElectronicMarket Forecasters"; Chambers, John
 Saivision Consulting Group, Inc.; "Embedding Programmable Logic in SoCs – An Implementation Example"; Duggirala, Mike; January 2002
 IC Insights, Inc.; "The McClean Report"; July 2002