How Sun reduced cost /supply risk by moving to COT

The company continues to engage ASIC suppliers who also source some foundry silicon, but this does not provide the same cost and supply-risk benefits of directly sourcing silicon from the foundry. Cost savings are achieved through lower foundry wafer costs as well as lower package substrate, package assembly and test costs. While ASIC suppliers can provide access to foundry silicon, they can't afford to pass the full price savings on to their customers. Without some mark-up, ASIC suppliers cannot maintain their own design and manufacturing infrastructure. Depending on the volume and complexity of the ASIC designs, this mark-up may still be a good value proposition for access to broad, deep, or specially skilled silicon development and manufacturing infrastructure. But for many ASIC designs where the required technologies have become more widely available, the ASIC mark-up may not offer sufficient value.

Supply risk is reduced by separating intellectual property development from silicon sourcing. Any custom IP developed at the physical/circuit level with an ASIC supplier becomes jointly o wned IP. From the perspective of a system house, this physical IP is essentially single-sourced. Any single-sourced IP is susceptible to supply continuity risk.

In a COT business model, IP development is either owned in-house or licensed from an entity separate from the manufacturing entity. Whether home-grown or licensed, separating IP development from manufacturing increases silicon sourcing options. To provide this type of supply-risk reduction, an ASIC supplier would have to not only source silicon from a foundry, but also commit to port hard IP to other foundries as needed.

There is some discussion of process-matching between ASIC and foundry fabs, but it's not clear that process-matching will work well for the unique device design characteristic of complex I/Os and phase-locked loops (PLLs). Although the historical ASIC business model has not supported the porting of hard IP between fabs, Sun expects this to become more prevalent in the future as ASIC suppliers continue to outsource t o the foundries.

COT elements

With this industry shift, the main motivation for COT would switch to a cost-driven model, with the supply continuity risk of the IP being contractually mitigated. This would end up being a hybrid model encompassing the benefits of both the historical ASIC engagement and the current COT model. The company's COT strategy has three major thrusts that leverage our microprocessor CAD and test/FA investments to varying degrees:

• Libraries. Several elements of Sun's technology and system interface strategies pose challenges that do not make off-the-shelf and microprocessor libraries an option. The COT group works with an outside IP provider to develop custom COT libraries. These libraries include high-performance I/O and analog libraries implementing Sun's proprietary system interface. Also, included are high-performance, high-density, highly manufacturable digital logic libraries that meet specific product performance requirements on COT-t argeted technologies.
  
  
• Design flows. The applicability of microprocessor design flows to ASIC design continues to drop as less and less processor logic is synthesized. The COT group has been able to leverage processor CAD tool licenses and signal integrity flows, but the primary design flow has been independently developed and geared toward fully synthesized SoC designs.
  
  
• Silicon manufacturing. The COT group includes already-existing, extensive ASIC package development and reliability expertise to bring up our offshore manufacturing work. We heavily leverage Sun's investment in test/FA equipment and expertise to augment our manufacturing capabilities.

Of the three primary COT development areas, library development and prove-in has been the most expensive and time-consuming element. This reflects the company's system/silicon development methodology that heavily emphasizes pre-silicon system simulation of all system interface IP, silicon prove-in across a full p rocess distribution of all new IP prior to qualification in systems and extensive work to correlate circuit and timing models with silicon.

This approach is geared to produce high-quality devices with ample yield across a full process distribution. The heart of silicon quality lies in the quality of the library development. No design or manufacturing process, no matter how rigorous, can make up for incorrect, poorly designed, or poorly characterized libraries.

Much has been said about the relationship between COT design and deep-submicron timing closure. There are two common myths. One is by going COT and gaining control over physical design, layout timing closure problems will be eased because logic synthesis and place-and-route will be performed by the same engineers. The second myth is the advent of all-in-one physical synthesis tools simplifies the ramp into COT by reducing the upfront investment needed for physical-design licenses and flow development.

COT's expanded control ove r physical design is a double-edged sword: more physical access for timing closure comes at the expense of increased yield responsibility (system/package interface, signal integrity, timing accuracy, and manufacturability to name just a few). While many of the latest physical synthesis tools do a much better job at handling signal integrity and timing accuracy than previously unintegrated tools, they only work as well as the library and technology collateral sent into them. High-quality VLSI designs do not come flying out of all-in-one CAD tools without ample silicon legwork backing them up.

In COT as in ASIC design, the best timing closure results will be achieved by one engineer optimizing the design from front-to-back. However, it is not clear that COT affords any greater opportunity for unified front-to-back work than an optimized ASIC engagement. The days of a straightforward ASIC netlist hand-off were long gone before the advent of physical synthesis tools or COT supply chains.

For the last five years, the company's ASIC hand-offs have included collateral such as layout timing constraints and floorplans. Further crafting the ASIC hand-off to encompass physical synthesis is the next step in the natural progression of the hand-off model to handle very deep submicron timing. Developing a COT supply chain for system ICs offers significant cost and supply-risk-reduction benefits beyond those achieved by simply sourcing foundry silicon through an ASIC supplier.