Tooling critical to project success
By Bob Dahlberg,Vice President of Marketing, ReShape Inc., Mountain View, Calif., EE Times
December 11, 2002 (10:00 a.m. EST)
ASIC customers are growing more dissatisfied with their ASIC vendors every day. It is not uncommon to hear ASIC customers lament that piece-part prices are high, the parts come back working at half the target speed and the time it takes to receive them is unpredictable. These are the same complaints captive-semiconductor customers had in the early 1980s.
Customer-owned tooling (COT) is at the top of the list for most companies looking for an alternative to application-specific ICs. Will COT replace ASIC, as ASIC replaced captive fabs 20 years ago? The answer lies in weighing risk and total cost. An attraction of the ASIC business model is that the ASIC supplier owns the technical risk associated with physical design through sample and production parts. Because ASIC vendors subsidize the nonrecurring-engineering charge in the hopes of volume production, they take on the customer's business risk as well. In the COT model, the technical and busines s risk is entirely on the customer's shoulders. Anyone experienced in the complete COT life cycle knows it is a risky proposition. Veterans have been bitten by costly mistakes-some have caused the death of enterprise. These mistakes manifest themselves as schedule slips and chip respins.
Pittiglio Rabin Todd & McGrath, a management consulting firm in Mountain View, Calif., has benchmarked new-product design processes in many high-technology sectors, including semiconductors. Its most recent study showed that poor management-related practices accounted for 46 percent of the reasons chip projects slip: Poor resource planning and late-changing specifications top the list. Technical reasons account for only 39 percent of the slips. The research has also shown that while the average project's actual time-to-market typically slips 30 percent from plan, the gap in the schedule performance between average and best-in-class projects remains wide, leaving ample room for improvement from better project manageme nt.
Numetrics Management Systems (Santa Clara, Calif.) has been doing chip design benchmarking for both application-specific standard products (ASSPs) and ASIC designs for many years. It has found that 85 percent of the chips that tape out have to be respun. The primary technical factor by far is inadequate functional verification. Functional verification is the customer's sole responsibility in both the ASIC and COT models. Numetrics has found that the second biggest factor causing slips and respins across the semiconductor industry is poorly executed physical design due to such effects as noise, slow paths, clocking and IR drop. Poor physical design is a major reason for the schedule slips that ASIC customers experience, and the same is true in the standard-product business.
The entire industry is grappling with this issue. Whether using an ASIC or COT model, companies must aggressively overcome poor management, inadequate functional verification, and inept physical design. This year's mana gement mantra is to "focus on what you do best, and outsource the rest." But since management can't be outsourced, companies are advised to instill a disciplined project work flow with clear checkpoints and criteria for moving forward.
On the technical side, since product function equates to product value, the customer must own functional verification. Physical design is a task whose value is independent of creating competitive advantage-other than on time, on spec-and has been outsourced for years via the ASIC industry. Competent engineers, not tools alone, mitigate technical risk. No one thinks that a verification tool can automatically perform adequate functional verification. However, in the implementation space-i.e., synthesis and physical design-teams are falling prey to the EDA vendors' siren song of RTL-to-GDSII pushbutton solutions.
Experienced front-end designers know that good synthesis results don't come from pushing buttons; and this is even more applicable in physical design. Th irty to 50 percent of the physical-design engineering effort is creating the pad ring. The same can be said of system-on-chip (SoC) block assembly. Tools work great on blocks, but fall short when it comes to chip assembly.
The EDA industry's "pushbutton" myth has given rise to another myth: the "tall, thin engineer." This able-bodied engineer is purported to be able, through the magic of physical synthesis and single data models, to span the register-transfer-level (RTL) and GDSII worlds. Recently we heard of a first-time COT customer's tall, thin engineer that had documented a 12-page synthesis flow. That seems credible. But his physical-design flow was five lines: "Verilog in, close block timing, top level-route, verify, GDSII to TSMC." Physical design is much more complex: It involves many more steps, and requires a multiplicity of tools. This tall, thin engineer is steering his company to chip design failure.
Companies require three separate areas of competence and expertise: functional d esign, functional verification and physical design. Experienced COT companies may have experimented with the tall, thin engineer, but now know that it is a rare individual that can span any two areas, much less all three. ASIC schedule unpredictability comes from using an out-of-date physical-design methodology. ASIC vendors have employed a "throw it over-the-wall" approach to physical design for years. (The "over-the-wall" for test broke down long ago; now the front-end design team owns design-for-test.)
To regain predictable schedules and performance, companies must employ a concurrent-design style, whereby the front-end design team and the physical-design team work in parallel. This is the design style that microprocessor teams employ to realize 2-GHz performance, while the COT market struggles to deliver 200 MHz. Concurrent design requires a huge investment in physical-design flow development. The savvy customer will look for vendors-either ASIC or physical-design house-that employ concurrent des ign, or for people who have built concurrent-design flows. A recent development is the emergence of the physical-design factory.
For example, ReShape is developing advanced design flow automation software to embody and automate the best practices of expert physical designers. The ReShape physical-design factory relies not on huge teams of people, but on automation, enabling ReShape to build full-chip GDSII in less than 24 hours. Full-chip timing and area information (not simply one block) is available very quickly to the front-end design team. This early insight into full-chip physical design issues enables predictable design schedules.
The obvious attraction of COT is a lower cost of goods sold. ASIC companies are now buying wafers from foundries, so it is natural for ASIC customers to ask, "why not cut out the middleman?" Not only are advanced process technology wafers available, everything else you need to produce a complex IC is available at competitive prices, too. However, the pathway f rom netlist to sample parts involves building an infrastructure composed of tools, people and methodology.
The biggest outlay is for tools. A minimum "starter" physical-design and design-for-test tool seat is about $1.5 million, but by the time the project is over, you will have spent $3 million to $5 million. You'll need a team of about five to eight engineers to set up a design flow, manage intellectual property and build the chip, at a cost of at least $1 million per year. For companies doing one to three chips a year, it is cheaper and less risky to outsource the physical design. Outsourced physical design will range from $250,000 to $2.5 million per chip depending on the chip's complexity and performance, and the vendor's competence. Silicon IP usually comes at no extra charge in ASIC, but has to be purchased in the COT model.
The typical cost of a mask set for 130 nm is $750,000; this cost can be cut down by a factor of four by going on a shared project "shuttle." Shuttle chips have to conform to a specific size, commonly 5 x 5 mm. The cost associated with back-end supply chain operations includes a plethora of details managed by the ASIC house, whose costs become the direct responsibility of the COT customer.
A lower-cost alternative for the captive team is outsourcing, since the outsourcing vendor's cost can be spread over more projects. Historically, all these costs have been included in the ASIC supplier's NRE charge and production chip markup. The COT customer has to pay these up front charges at market rates, and be paid at the time service is provided. There is no free lunch adopting COT over ASIC. COT customers clearly gain more design freedom, more visibility into schedule and lower piece-part costs. However, they must accept increased risk in managing physical design and the supply chain. In the meantime, it is possible that savvy ASIC suppliers will overcome their physical-design inadequacies.
See related chart
See related chart
See related chart