That Moore's Law drives complexity is axiomatic. That the growth of complexity presents novel challenges to device designers and architects is not news. But why this is the case is less obvious; the answer offers some tantalizing indications of the course complex device architecture will take in the next few years.
Complexity is commonly considered synonymous with gate count, but that tells only half the story. The other half concerns topology: how the smallest elements making up a design are connected, and in what patterns or structures. As the sheer number of components on a device rises, so too do the topological diversity and intricacy of the device's organization.
Designers can confront this topological complexity haphazardly, using ad hoc cut-and-try methods that have worked adequately in the past. But it's far better to approach it systematically, mobilizing the growing body of formal theory and practice, which tells us how complex topol ogies actually behave and how they can be optimized.
What the industry is discovering now has been well-known to theorists for a long time: At a certain point, ad hoc methods applied to sufficiently complex topologies give rise to insoluble contradictions. At such a point it becomes imperative to abandon informal, haphazard techniques, bite the bullet and adopt new formal approaches.
The semiconductor industry is in a crisis that has in part been caused by the ineffectiveness of old approaches in the face of rising complexity.It is clear that the complexity-driven costs and risks associated with turning tens or hundreds of millions of transistors into reliable, cost-effective, timely products must be contained, or else the semiconductor industry will fail to deliver to customers the gains promised by advanced deep-submicron processes. It is also clear that this battle must be waged simultaneously on the front of device architecture and on the front of design methodology.
A major architectural shi ft is required in order to overcome the dual challenges of advanced deep-submicron (DSM) geometry and material science, on one hand, and those of timing, verification and logical coherence on the other. Platform architectures can offer optimizations that balance complex functions-required in similar form by large numbers of designs-with the need of customers to achieve differentiation through proprietary custom logic. The problem of complexity is mitigated when those platform architectures are realized in technologies exploiting late metal process steps to reduce the time and risk of bringing complex designs to market.
More time to design
This balance between complex function and reduced risk means that customers no longer must bear the difficult integration, timing-closure and verification burdens associated with very high-performance designs. Instead, modern platforms use high-level, pre-optimized blocks to guarantee compliance with requirements, freeing designers to focus on unique, differe ntiating innovations.
New tools and methodology, based on the formal advances mentioned earlier, are now being introduced; they allow complex blocks representing abstracted firm or hard functions to be integrated in structures whose collective timing and logical behavior are predetermined to meet strict operational criteria. Thus, customers needn't undertake the costly task of independently verifying that the intellectual-property blocks will conform to specifications in a new design, and are freed to concentrate on adding value where they have special expertise.
This balanced sharing of responsibilities between manufacturers whose IP and methodology enable maximum exploitation of DSM capabilities and their customers that focus on unique added value is a harbinger of platform-based design.
The future of semiconductor design lies in adopting a platform approach to taming the costs and risks of complexity. Such an approach, involving higher levels of abstraction, offers customers access to complex high-performance functions while insulating them from the increasing difficulty of reliably implementing such blocks in advanced processes. In addition, the customers' value-adding design activities are no longer held hostage to growing topological complexity.
Chris Hamlin is Senior Vice President and Chief Technology Officer of LSI Logic Corp. (Milpitas, Calif.) Hamlin has a BA in history and mathematics from the City College of New York and holds a PhD with distinction in oriental studies from the University of Pennsylvania.