How FPGA technology is evolving to meet new mid-range system requirements

Ted Marena, Microsemi
embedded.com (May 07, 2018)

Multiple trends are sending FPGAs down two distinct development paths. On one path, FPGAs are being optimized primarily to accelerate data center workloads. The data center focus is the next holy grail that the larger vendors are laser-focused on. On another development path, there are the traditional FPGA markets of networking, cellular infrastructure, defense, commercial aviation, industry 4.0 and medical. In these markets many engineers feel they are being abandoned. Their development challenges are quite different than the data center focus that the large vendors are focusing on. Here, designers face an increasingly difficult balancing act as they try to achieve a combination of low power and cost without sacrificing performance and security. Navigating this balancing act requires looking at FPGAs in a new way, using new process technology choices, fabric designs, transceiver strategies and built-in security measures. This has led to a new class of mid-range FPGAs that deliver new capabilities for traditional FPGA developers to leverage.

New Process Technology Choices

One way to reduce power while optimizing the cost of mid-range FPGAs is through the use of new process technologies. For example, using Silicon-Oxide-Nitride-Silicon (SONOS) non-volatile (NV) technology on a 28nm technology node provides a lower power advantage as compared to both SRAM-based FPGAs at the same or even smaller nodes. Previous-generation non-volatile FPGAs using 65nm-and-older floating gate NV technology are more expensive than SONOS. Whereas floating gate technology requires 17.5 V to program using large charge pumps that consume a substantial die area, SONOS technology requires only 7.5 V for programming, so charge pumps can be smaller. This technology enables a smaller die size and contributes to a more cost-effective device.

SONOS technology delivers these benefits by using a single poly transistor stack with a non-conductive Nitride dielectric layer (silicon-nitride, Si3N4) as the charge storage element (see Figure 1). Using this approach, only a very small amount of charge will be lost in proximity to any defect that may exist in the bottom oxide. Because the stored charge is non-mobile in the insulating Nitride layer, most of the stored charge remains where it is, intact. A thinner bottom oxide can be used compared to the floating gate technology, and it can be programmed with lower programming voltages (~7.5 V) and smaller charge pumps. Fewer transistors are required with SONOS than with an SRAM memory element.

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