Mixed-signal design flow enables RF CMOS chip
By Rami Ahola, EEdesign
February 28, 2003 (3:56 p.m. EST)
Spirea AB is a Swedish fabless semiconductor company developing highly integrated low-power, low-cost radio solutions for the Wireless LAN and PAN markets. This article describes how we assembled a design and verification flow, using off-the-shelf design tools, that enabled leading-edge CMOS design techniques for RF, mixed-signal and digital designs.
The continuing growth in multi-standard wireless communications is driving steadily increasing demand for cost-effective radio components. To meet these demands, Spirea needed to employ a design and verification flow consisting of standard design tools. We did not have the option of developing proprietary solutions to address the dramatic complexity of high-speed RF design. With our design flow, we have been able to exploit the advantages of CMOS technology in RF and mixed-signal design, utilizing highly optimized design techniques at the architecture, block and transistor levels.
Inside the Trip leTraC
Spirea recently started sampling its new TripleTraC radio IC product, the first multi-standard transceiver combining 802.11b, 802.11g and full band 802.11a on a single chip. This dual-band chip includes two RF front-ends, one running at 2.4 to 2.5 GHz and one at a very fast 5.1 to 5.9 GHz. This is a pure radio IC, which does not include baseband functionality or a MAC layer. TripleTraC is the world's first fully integrated CMOS combo WLAN transceiver. The development process, which is a company wide venture, began approximately a year ago.
TripleTraC was developed for applications requiring low power, small form factor and low implementation costs, including network interface cards, access points, notebooks/PDAs, and AV applications. Its low power consumption makes it ideal for battery-driven applications. The design provides a high degree of integration, while significantly reducing the number of external radio components typically required with other solutions. TripleTraC is fabricated i n UMC's 0.18µm RF CMOS technology and is QFN packaged for optimal RF performance and small form factor.
The primary objectives when developing the TripleTraC chip were to maximize performance, while minimizing power consumption and price. Using the CMOS process and a very small die area enabled the creation of a very cost-effective chip that is very competitive in power consumption.
Assembling a mixed-signal/RF design flow
The Spirea design flow consists of a mixture of commercial tools. On the front end, we use Design Architect-IC from Mentor Graphics for schematic/design capture and mixed-mode simulation setup. This enables us to use VHDL-AMS extensively for functional verification, connectivity checks and the like. Using VHDL-AMS, we can actually run a full power up sequence, receive, transmit, and power down. For sub-system verification, such as PLLs, we use VHDL. The Design Architect-IC design cockpit enables us to manage IP and design data in multiple formats.
For daily simulati on work, we use Aplac's Fast RF-IC Module. This tool provides enhanced harmonic balance analysis methods optimized for RF IC Design. We use Aplac in situations when the designer tweaks one transistor, or makes a small modification and needs to run a quick simulation. For verification of larger components, we use the Eldo RF tool, which is part of Mentor's ADVance MS single-kernel simulator.
For physical layout, we use Mentor's IC Station, and for our DRC and LVS checks, we run Mentor's Calibre. Before setting up our design environment, we received a 0.18um mixed-signal/RF design kit from UMC, which contained Calibre rule decks, device models and process definition files.
Finally, though the majority of TripleTraC circuitry is analog and was developed at Spirea, we did use digital standard cell libraries from Virtual Silicon.
Architecturally, the biggest challenge in the development of TripleTraC was the fact that the chip contains two radio transceivers, one for the 2.4 GHz band and one for the 5 GHz band. Our mandate was to achieve maximum hardware sharing so that we did not have to build two separate radios on the chip. To realize this objective, we developed separate front-end structures for the radios, and shared the rest of the circuitry.
Figure 1 -- TripleTraC
From the circuit level perspective, designing at close to 6 GHz presented some new and interesting challenges. The uppermost part of the 5 GHz wireless LAN band runs at 5.8 GHZ, and at this speed, things start to get difficult. Layout parasitics become more and more important and model accuracy can be somewhat questionable. The models we get these days are generally pretty good, but you still have to know what you are doing with them when using them at these frequencies.
We created our own models for passive devices, but for active transistors, we relied on foundry RF models, which were included in the UMC/Mentor Graphics design kits. The foundry models for passive devices were non-physical, fitting to experimental data, which made them fundamentally non-scalable, so we developed a physics-based model that is scalable in device size (widths, lengths, resistors, capacitors).
Most companies rely on foundry models completely, but in the creation of high-speed RF designs, our experience has showed that this is not adequate. Unless one is completely familiar with the models, it would be difficult to know what the pitfalls are. We have seen the need to at least verify all the foundry models we get. We basically do this by comparing, measuring and simulating all of the data. Though there are always some slight differences, when significant differences are discovered and further investigation is necessary, we can end up doing a lot of characterization by ourselves.
Device generators for productivity enhancement
The physical implementation of mixed-signal designs, especially those containi ng high-speed RF circuitry, is a very hands-on proposition. In the case of TripleTraC, approximately 4,000 analog/RF devices had to be created by hand; all of the analog layout is full-custom. One method we have employed that has saved inestimable time is the use of parameterized device generators.
Device generators are quite valuable, considering the time it takes to lay out a block. In terms of number of iterations, with device generators, we are assured that we will get it right the first time. We rely on them heavily, especially for devices such as capacitor, resistors, inductors, MOS, and guard bands-just about every analog device there is.
Though it is difficult to accurately state exactly how much time is saved when comparing the use of device generators to hand layout, the difference is enormous. Depending on the device, using device generators can provide productivity gains somewhere between 10 and 100X. For the TripleTraC product, it was critical that we got the RF transistor layouts corre ct so that the layout exactly matched what was characterized by the foundry.
Figure 2 - Inductor device
Additionally, specialized devices such spiral inductors would take literally forever to draw out manually, and the generator produces them in about a half a second. Further, the device generators create scalable devices, which allows us to resize them to meet our needs, but with the confidence that the devices will remain DRC-correct.
Another way we've been able to achieve productivity gains is through the adoption of schematic-driven layout (SDL). SDL has been especially valuable for designers with limited experienced in layout. For the very experienced layout person, he/she can pretty much look at the schematic and place the components, knowing which device belongs where and where the connections need to be made. But if you have people on your team who do not have years of layout experience, SDL definitely increases their productivity. Users get few, if any LVS problems; the rubber bands are in place, so the designer knows where things need to be connected.
Figure 3 - Schematic-driven layout
To ensure cost containment, first pass success was paramount in the development of TripleTraC. This being the case, our choice of physical verification tools was quite important. Since Calibre is used internally for signoff at UMC, it was really our only choice. Had we used another tool, we would have had to convert the rule decks, which could have possibly resulted in lost or corrupted data, and we would not have been 100% confident when we went to fab.
We're currently using Mentor's ICextract for extraction. We've found that this tool fits pretty well into our design flow. After we do layout, an extraction run is performed, after which we back-annotate to the simulation viewpoint and simulate with exactly the same testbench as before extraction. On designs such as the TripleTraC, which run at such very high frequencies, parasitic extraction is an absolute must. For example, in VCOs, parasitics that are unaccounted for can easily shift resonance frequencies by hundreds of megahertz.
Using a standard design and verification flow, and exploiting CMOS RF and mixed-signal fabrication, we were able to produce this very fast chip and achieve silicon success in the first pass. We did not have to resort to process technology or proprietary design tools to achieve the low power consumption and high speed we achieved in TripleTraC. Using a standard design flow and UMC's 0.18um RF CMOS process technology, we found means by which to maximize productivity, and the project was completed on time, within budget.
Rami Ahola received the M.Sc. degree in electrical engineering from Helsinki University of Technology (HUT), Helsinki, Finland, in 1997. From 1996 to 2001 he worked as a research enginee r at the Electronic Circuit Design Laboratory at HUT. Since 2000, he has been with Spirea AB, Stockholm, Sweden, where he currently works as design team manager for the TripleTraC 802.11a/b/g combo radio chip.