SAN JOSE, Calif. Faced with excess manufacturing capacity and complex chip design challenges, Taiwan's biggest pure-play foundries are taking a fresh approach to the way they manage intellectual property as they seek to burnish their image as the chip industry's trendsetters.
While the ultimate goal is to manufacture more finished wafers, recent moves by Taiwan Semiconductor Manufacturing Co. and United Microelectronics Corp. suggest a more ambitious effort is under way. TSMC has begun distributing its cell libraries through external companies; UMC has overhauled its intellectual-property (IP) catalog. And both foundries are looking to create IP cores tied to their own manufacturing processes.
If all goes to plan, the foundries could wind up becoming meccas for the chip industry a common point where chip makers, design houses, IP vendors and software tool providers coalesce. "The term is reaggregation of the the supply chain," sa id Andrew Moore, marketing manager for design services at TSMC North America. "It's a funnel that gets wider as you go up."
The foundries have sound reasons for wanting to be at the receiving end of the funnel. As they prepare to shift to 90-nanometer process design rules, many chip designers will have no choice but to purchase more third-party IP to complete their designs.
"With the amount of gates you can physically put on a die at 90 or 65 nm, there's no hope at all of going back to the way designs were done five years ago," said Rich Wawrzyniak, an analyst at Semico Research Corp. "The use of IP blocks to flesh out designs at this point is the only way to go."
Yet the IP market is still in a chaotic state, and fewer companies designing chips have the means to keep tabs on the vast network of IP providers. At the same time, more companies are under the gun to meet more-compressed product deadlines.
One way the foundries are responding is by wading deeper into the intellectual-property busi ness. TSMC recently said it would distribute its cell libraries through three external companies, with Virage Logic Corp. the first to be announced, and Magma Design Automation Inc. identified as its second distributor last week. TSMC said the move is intended to give customers more choice of libraries, and to shift the design and support to companies that are set up for those tasks.
"We're a foundry, so we're not equipped to do 24-hour, Web-based, around-the-world support like a partner such as Virage. They have a couple of hundred people who do that as part of their culture," Moore said.
The choice of Virage (Fremont, Calif.) shows how difficult it can be to distinguish partners and competitors in the IP business. Virage recently acquired its own cell libraries that it sells to its own customers; it will give away the TSMC standard-cell and I/O libraries for free.
Yet Virage is likely to collect fees from TSMC in exchange for passing those libraries on to c ustomers of its workhorse memory compilers. Moore said that such a financial model "makes sense," though neither he nor Virage executives would discuss details of the financial arrangement.
Such a deal might work for Virage, but it makes little sense for reigning library provider Artisan Components Inc. (Sunnyvale, Calif.). Artisan too collects fees from foundries for libraries it gives away to its customers, but the company has no interest in distributing IP that competes with its mainstay library business.
"We can provide the identical solution for about 16 manufacturers; 12 of them are pure-play foundries," said Mark Templeton, Artisan's president and chief executive officer.
Even so, TSMC and Artisan said the situation has not caused a rift in their relationship, evidence of how much their interests still overlap. As the world's biggest foundry, TSMC represents a sizable revenue source for Artisan, which will keep distributing TSMC's I/O cells as it has before. And TSMC recognizes that Artisa n's libraries are used widely in the design community.
"We have a great relationship with Artisan," Moore said. Despite the new relationship with Virage, "We're not going to pull back from [Artisan]. Frankly, a lot of customers are using them."
TSMC rival UMC, meanwhile, is also looking to improve the way it handles IP. In coming weeks, the company will announce a revamped IP catalog it developed with the help of software vendor Synchronicity Inc. (Marlboro, Mass.). Using a Web portal, UMC's customers will be able to evaluate libraries and IP blocks from participating IP vendors and pose questions to UMC engineers.
The one thing users of the Web portal won't be able to do is buy the IP outright through UMC. Specifications, behavioral models and testbenches can be downloaded freely, but designers will have to negotiate directly with the IP vendors as they always have. Different IP vendors have different licensing terms and UMC isn't about to step in and rewrite the rules.
"In the end we're a manufacturing company," said Alex Bi, product marketing manager for UMC USA (Sunnyvale).
Cores under development
Though there seem to be limits in how much they can participate in the IP trade, foundries are becoming less skittish about offering their own homegrown IP cores when it suits them. UMC, for one, is considering developing blocks of mixed-signal cores for customers as a way to usher in more designs earlier than it would otherwise. Phase-locked loops, A/D converters and USB transceivers are among the possibilities.
"Mixed signal is tied to a specific process technology," said Benson Lee, director of product marketing at UMC. "It takes a lot of time to do the tweaking and modification. That's why we're considering doing this internally."
TSMC has already kicked off an IP development effort of its own, with offerings such as a Bluetooth front-end core for its mixed-mode 0.18-micron process. Moore said TSMC is planning to offer more cores designed for its process technology.
"Doing a 6-bit A/D converter for audio doesn't make sense for us, but doing a USB 2.0 [core] that pushes the envelope of our process and models makes sense for us," he said. "It's not for competitive reasons, although once we get stuff done we're going to share it. The reason we do IP is the same reason we do libraries: to make sure that designers can execute on the process."
Still, TSMC and UMC will continue to lean on the dozens of third-party IP suppliers that participate in their respective shuttle programs. These efforts help the IP providers to qualify their cores for manufacturing and give the manufacturers a means to tweak their design rules.
In some cases the foundries seek closer ties to IP vendors, particularly those providing embedded memory, which often takes up half the die area of a system-on-chip. TSMC and, more recently, UMC have signed deals with Mosys Inc. to provide 1T-SRAM as a standard alternative to embedded SRAM. Mosys, in turn, collects licensing fees and royalties dir ectly from the foundries.
TSMC's decision to work more closely with Virage is further evidence of the importance of embedded memory, which is often closely tied to a process technology and can have a significant effect on wafer yields. As such, Virage expects to be the first IP company to field test chips on TSMC's newest 90-nm design rules, said Adam Kablanian, the president and CEO of Virage.
Some observers, however, questioned the motivation behind some of the IP efforts. Some see TSMC's program to give away its cell libraries as a thinly veiled attempt to lock more customers into its own manufacturing technology and discourage defections to competing foundries. Handing over the distribution rights to partners like Virage is just passing the buck, said Semico analyst Wawrzyniak. "TSMC is still the fly in the ointment, but Virage will take the heat," he said.
Artisan's Templeton agreed that customers want the freedom to choose their manufacturer. "Our customers really don't want a proprietary solution from a manufacturer. One of the reasons is that they want flexibility. I think people have pointed that out with the TSMC product," he said.
TSMC's Moore, however, said the subject "never arises" with customers. He added that they are less concerned about shopping for foundries and more worried about meeting product deadlines. "There was a study not too long ago showing that missing a market window by three or four weeks costs in the tens of millions of dollars. That's what they care about," Moore said.
Indeed, some companies are betting that customers' preference for multiple foundry sources is falling by the wayside as chip design gets more complex. Faraday Technology Corp., an ASIC provider hat was spun out of UMC, thinks the days are gone when a fabless chip company could develop different versions of the same design to negotiate better prices from its primary foundry. Faraday, which is putting a heavy emphasis on building a broad IP portfolio, said it wil l continue to work with UMC exclusively, a strategy analyst Wawrzyniak called "a disaggregation model in reverse."
Faraday thinks its strategy works because certain aspects of the chip design such as the mixed-signal portion or the memory are getting so sensitive to the process technology that the cost of tweaking the design for another foundry becomes untenable. "Once you go to a foundry, especially as you go to 90 nm, it's going to be very costly to go to another foundry," said Mike Shamshirian, senior sales manager for Faraday's IP business unit.
Many IP vendors are struggling with the same issues and won't have the luxury of working with multiple fabs, he said. A better plan is for companies to broaden their IP portfolios and strengthen their design service efforts. "IP is becoming equally important as the fab itself," Shamshirian said. "If [customers] can get it from one player that's the best solution. They don't want to worry about integration issues when they tape out."
Nei ther do the foundries, which are becoming more sensitized to anything that stands in the way of a chip going to volume production. As all roads lead to them, foundries are in a unique position to clear a path for the chip industry in its drive to embrace more IP. The trick is balancing competing interests and knowing where to draw the line.