Layout compaction accelerates SoC design through hard IP reuse
By Coby Zelnik, Senior Vice President, Business Development, Sagantec, Fremont, Calif., EE Times
December 19, 2002 (10:47 a.m. EST)
In enabling multimillion-gate SoC designs, the latest process technologies have widened the gap between manufacturing capabilities and designers' abilities to quickly put together these complex devices. Reuse of existing intellectual property (IP) helps close this gap and enables companies to meet tight time-to-market objectives, despite rising demand for increased SoC differentiation. Among IP reuse strategies, reuse of silicon-proven physical designs, or hard IP, is particularly effective in meeting the growing need for specialized, custom blocks for high-performance digital, analog or mixed-signal functionality.
In the past, however, the difficulty of migrating hard IP to new manufacturing technologies has precluded its use in all but very high-end devices. Today, a new generation of compaction-based EDA tools and methods has emerged that better equips designers to exploit custom hard IP blocks in complex SoCs, delivering highly differentiat ed silicon within the constraints of increasingly tight product schedules.
Hard IP provides the fully designed, proven and tested circuitry needed to serve the increasing array of applications that require high-performance digital or specialized analog/mixed-signal functionality. Traditionally, however, hard IP has been difficult to exploit easily in SoC designs. Hard IP represents a custom design that has already been implemented in a physical design, verified and delivered in a GDSII representation. Consequently, reuse of hard IP means migration of that GDSII representation to a new process technology due to the rapid pace of advances in manufacturing capabilities.
Manipulating this type of data has presented a significant challenge to engineers, limiting widespread reuse of hard IP. In its GDSII form, today's advanced hard IP can easily comprise gigabytes of data. Each of the millions of polygon edges described in the physical design have been sized and placed precisely to meet the part icular technology design rules and device performance objectives. In turn, hard IP migration requires the ability to deal with every polygon in the file, adjusting each one in size and in relative spacing with respect to the millions of other objects in that physical design. With GDSII files of this size and complexity, manual efforts have become impractical. Even a single mistake can lead to design rule violations resulting in a non-manufacturable design.
In the past, design migration most commonly occurred through a linear shrink process, where every feature was reduced in size and spacing all scaled by some uniform factor. While such simple shrinks were successful in previous technology generations, they have become ineffective with nanometer technologies at 0.13 µm and below. Here, because of various physical effects associated with the manufacturing process, each layer and object is scaled differently, reflecting its specific manufacturing tolerances and sensitivities.
In addition, the relationships between polygon size and the characteristics of the underlying elements, such as interconnect characteristics, threshold voltages and corresponding transistor conductance, are dramatically nonlinear. Engineers can no longer expect that a straightforward uniform shrink of feature sizes will yield manufacturable devices or maintain circuit performance and behavior, even in purely digital designs.
With today's nanometer technologies, high-performance digital circuits increasingly behave like analog circuits. As such, migration requires that individual instances be accurately and individually sized based on specific operating conditions. Similarly, the width and spacing of wires requires more specialized attention with advanced technologies. Because interconnect significantly impacts circuit performance in these technologies, migration now require s careful analysis of each wire segment. Wire segments need to be sized properly, paying strict attention to such issues as current density, possible dynamic voltage drops and potential electromigration problems. Hard IP migration requires an intelligent compactor that can address all these issues in detail, carefully and methodically adjusting individual instances, while still maintaining the IP's basic physical design architecture and topology.
For digital hard IP, automated migration methods need to address each individual transistor or even each individual edge of diffusion or poly that makes up the transistor. Similarly, these methods must handle the individual metal layer polygon that is part of a particular conductance segment. All the while, any automated compactor needs to maintain design hierarchy and topology, while accepting directives for sizing individual wire segments, conductor networks and active devices.
For analog hard IP, migration methods must deal not only with the fundamental design issues found in digital designs, but also with the specialized nature of analog physical design. Analog physical design is usually smaller in device count and die area than digital, yet analog sections often become the tricky bottlenecks that threaten schedule. This is because analog physical design demands strict attention to the manner in which individual circuit elements are designed and laid out. In an analog design, each element in the layout is placed, sized and oriented for a specific reason. Accordingly, analog IP migration methods must maintain that physical layout intent and existing relationships between each element and its neighboring elements.
Wire width and placement bring further concerns in analog migration - and provide very little tolerance for error. Any successful analog IP migration approach needs to pay close attention to determining the correct width needed to meet the specific current requirements for each segment. Furthermore, certain wires or subcircuit elements are often matched to others in analog designs. Accordingly, migration must match circuits not only in terms of the load that is part of the netlist but also in terms of the parasitic load associated with the layout. For example, if certain wires pass over the subject wire, the same number of wires with the same length and spacing must pass over the other matched net or element.
Any disruption to the layout, even those that would seem to make little or no difference, can make a tremendous difference in performance. These subtle issues of design intent are not captured at the schematic or netlist level, but only by the way in which the physical design was laid out. Any automated compaction technique must recognize this implicit design intent and preserve it when migrating the physical design to a new process technology.
Today, intelligent and powerful compaction tools for process migration are able to analyze physical designs and complete the myriad of de tailed steps needed to reliably and automatically migrate hard IP and other physical designs to new applications and process technologies. They can complete the very large number of individual polygon-level geometrical operations needed for successful hard IP migration. Likewise, a sophisticated compactor with built-in design rule checking and repair will accommodate fast adjustment to any previously migrated physical design when updates to design rules occur an inevitability when dealing with new process technologies.
With the availability of intelligent, powerful compaction tools, hard IP reuse has become an effective solution for meeting accelerated demand for more complex, differentiated SoCs within tight delivery windows. For leading semiconductor companies, such automated migration tools already provide a proven capability for migrating hard IP ranging from multi-gigahertz custom digital circuits in computer applications to high-performance analog and mixed-signal designs in communicat ions IC markets. As the industry moves toward increasingly advanced process technologies, the ability to leverage these tools will continue to provide a competitive edge in closing the gap between manufacturing and design.