Nanometer scale effects complicate IP characterization
By Graham Bell, Director of Marketing, Nassda Corp., Santa Clara, Calif. , email@example.com, EE Times
December 19, 2002 (10:22 a.m. EST)
To meet the growing demand for higher performance applications, SoC designers are integrating increased numbers of larger memory IP blocks on more complex devices. Embedded memory already accounts for a significant portion of SoCs today and promises to reach 70% of SoC content by 2005, according to Dataquest.
Even as larger memory blocks occupy a greater share of SoCs, the diversity of these blocks continues to expand, resulting in a rapid proliferation in the number and size of IP blocks. Each instance occupies a specific location and orientation, with routing and power connections that result in a unique dynamic operating environment for each instance. Accordingly, designers can no longer rely on traditional characterization methods that assume all instances are identical. Instead, each instance must be characterization separately and accurately.
Reliable verification results rely on the availability of accurate characterization data, yet designers often must deal with estimated values as traditional characterization methods reach the limits of their capability to deal with larger, more complex IP blocks. Increasingly, design teams are turning to more effective post-layout analysis methods able to provide accurate, instance-specific characterization data for IP targeted for nanometer technologies at 130nm and below. With the availability of rapid, accurate analysis tools, designers can more easily perform the kind of detailed characterization of individual IP blocks that underlie successful IP reuse strategies.
As with any IP, the accuracy of memory IP characterization data determines the accuracy of subsequent timing and power analysis of SoC designs that use that IP. Yet, IP consumers typically find that underlying approximations and limitations in traditional characterization methods too often require the use of estimated values for SoC verification. With traditional methods, IP developers have typically characterized only s ome combinations of compiler output, usually confining detailed characterizations to a representative combination of cell parameters such as number of bits per word, number of words and column multiplexing. Designers looking to use other specific compiler instances would be left to interpolate available characterization data to reach some estimates of performance for their particular memory instances.
Even available characterizations have typically provided incomplete timing and power results. Traditionally, characterization of larger blocks has been limited to netlists and critical paths rather than complete instances, because traditional circuit simulation tools have lacked sufficient capacity and speed for comprehensive analysis of entire blocks. Although this approach has produced satisfactory results for 0.25 µm devices and low-speed designs, it becomes ineffective for today's high-speed multimillion transistor devices targeted to nanometer technologies.
Traditional SPICE tools rea ch maximum capacity at about 50,000 elements, including transistors, capacitors and resistors. For their part, more recent "fast-SPICE" tools lose their speed advantages in post-layout analysis, because parasitics introduce coupling between nets, which invalidates the basic assumption of these engines that separate nets are uncoupled and can be analyzed independently.
Post-layout analysis with full parasitics is imperative to analyze the increased impact of nanometer effects like coupling capacitance and IR drop. Although coupling capacitance and IR drop introduced less than 10% error between predicted performance and actual silicon behavior of 0.25 µm designs, these nanometer effects contribute as much as 20% to performance of 130 nm designs and 40% for 90 nm designs. As a result, typical design guardbands of 15%, which were adequate for 0.25 µm designs, cannot pre vent timing faults in nanometer designs analyzed without inclusion of post-layout parasitics.
Coupling capacitance and IR drop are global phenomena that reach across signal and power nets. Consequently, critical path analysis methods using partial netlists will miss significant timing variations induced by nanometer interactions between the target path and circuit elements that lie outside the partial netlist. Furthermore, these cut netlist methods can not support effective power analysis, even as power becomes a metric of growing concern to designers.
Beyond these issues, the migration to more advanced process technologies adds further complications: Subtle manufacturing variations at different foundries can translate into significant variations in device characteristics. The existence of these variations drives the need for re-characterization with each migration of IP not only across processes but also across foundries for the "same" process technology node. Furt hermore, when the foundry choice has stabilized, process characteristics can still change: Even with a given foundry, the continuous process improvements found with new, leading-edge technologies create new performance parameters and dictate a need for rapid re-characterization to update characterization values.
In the past, re-characterization meant considerable delay while engineers plodded through hundreds of circuit simulations needed to analyze circuit performance at multiple points of interest. Today, each simulation becomes even more involved, requiring comprehensive analysis of signal and power nets including back-annotation of full post-layout parasitics to identify potential timing problems due to nanometer effects. Today's large memory arrays can easily result in flat netlists comprising millions of transistors with many times more extracted parasitic resistors and capacitors, surpassing the ability of conventional SPICE and fast-SPICE tools.
Newer circuit simulation tools like N assda's HSIM and LEXSIM circuit simulators use hierarchical methods to provide the required combination of speed, capacity and accuracy needed for effective characterization of complete memory IP instances. With these tools, engineers can simulate timing performance and dynamic IR drop across entire IP blocks at the transistor-level using full post-layout parasitics. Designers can use these tools with hierarchical netlists to simulate an entire memory array not only more completely but actually faster than possible with critical path methods.
As designers move to more advanced nanometer processes, comprehensive transistor-level post-layout analysis is essential for accurate characterization of IP. At the same time, precise IP characterization does not eliminate or lessen the need for full-chip post-layout verification and analysis. Instead, SoC designers can facilitate final verification by instantiating "known-good" instances into the design - removing subtle errors within the IP and leaving only t rue design problems to be uncovered and fixed. With the availability of more effective post-layout circuit simulation tools, design teams can more effectively leverage IP reuse in more complex SoC designs and increase confidence in their ability to achieve first-time silicon success.