Complexity is very high with multimillion-gate, IP rich designs in CMOS12, involving many components in the nanometer SoC manufacturing chain. Achieving First Time Silicon Success (FTSS) requires a complete solution, from available IP and cell libraries through to prototyping capabilities and production capacity. In addition, to ensure all milestones are met timely and cost-effectively, technological expertise must also be covered by the umbrella of proven and professional project management structures.
Through engineering expertise, a broad skill-set and early volume ramp-up, Philips is providing the technology for customers to establish early leadership in their markets. Clearly, it also proves the entire production chain is capable of rapid ramp-up from initial idea through to volume silicon production and firmly positions the company at the forefront of advanced CMOS process technologies.
The first key criterion for the crea tion of successful SoC designs in any new process technology is to have the IP available. Combining industry recognized leading embedded processor (ARM and MIPS) and DSP cores with a wide range of embedded memory options, complex and analog/mixed-signal blocks as well as advanced I/O functionality, the company's IP portfolio provides a complete toolkit to build CMOS12 designs. The range of IP includes coprocessors, DMA/SDRAM and Flash controllers and USB connectivity as well as market-specific modules such as LCD drivers and camera interfaces. However for all our design teams, a key ingredient for our customer success has been the capability to align this broad portfolio from both internal and external sources through a strong reuse architecture.
Specifically, for our advanced SoC designs, the ability to follow trends in high memory integration has become critical. In CMOS12 development, this area has been given particular attention, coupling Philips core expertise in enhancing low-leakage and hig h-speed memory with the tight integration and collaboration with memory complier partners to ensure the same reliability as in previous design generations. Continuous methodology enhancements to combat rising Soft Error Rate (SER) and the use of redundancy in 6T SRAM have enabled much higher low-leakage memory content in current CMOS12 designs, with up to 10 Mbits of SRAM. From the other performance perspective, access times sufficient for operating frequencies of 400-500 MHz have been achieved.
In addition, Philips' library technology group has enhanced master-client Built In Self Test (BIST) solutions, enabling customers to gain rapid access to the ever-increasing variety of memory instances on SoC products. Beyond the SRAM architectures we needed in CMOS12, the integration of eDRAM and 1T SRAM options on the same logic process with minimal additional metal layers for large on-chip memories have been realized, matching customers' target specifications.
Meeting FTSS criteria
One of Philips' strengths is in transferring know-how gained from previous CMOS process development to the next generation, enabling it to overcome the many challenges presented when implementing new processes. Many key ingredients of these challenges remain the same as previous generations, however they still require advances in methodology and an innovative design approach. Based on customer feedback and derived alternative solutions in CMOS18, we carried these amendments over to CMOS12 and will continue to do so in future generations like CMOS090.
The company's automated methodology for design kit generation has certainly helped quickly turn the 0.12 µm CMOS process into real silicon delivery. The whole development procedure has been intelligently aligned, linking tools to processes while incorporating a high degree of flexibility for new requirements. Based on a 'common source' concept, consistency between all design elements is ensured guaranteeing systems a high level of in-bu ilt quality a major reason behind the compatibility and time-to-market successes of CMOS12.
Addressed earlier in CMOS18 and VSC10, recurring Deep Sub Micron (DSM) issues in CMOS12 have been dealt with in a number of ways with a range of proprietary and recognized third-party tools, effectively beating the 'design tool productivity gap'.
For example, IR drop a problem accentuated in designs employing 1.2 V cores and crosstalk delays are offset through careful choice and implementation of analysis tools, while On-Chip Variation (OCV) tools detect timing discrepancies due to die variations caused by process, temperature or voltage differences. All of this is supported by state-of-the-art device modeling with MOS Model 11.
The newly introduced corelib 'Q' concept directs efforts at creating high-speed, high-density designs in a single package, offering 'mix'n'match' dual Vt options for optimum performance - impacting both synthesis and cell-design (footprint compatible standard cells) for place and route. To counteract slower run-times due to the large databases generated by complex SoC verification processes and timing-driven P&R, significant effort has gone into optimizing run-deck performance. This involved development of a powerful system infrastructure based around fast, parallel processing to ensure run-times are kept to a minimum.
Achieving FTSS has also required many new and novel approaches. One example, involving the integration and silicon qualification of I/O-library cells as part of a complete sub-system, has had a highly beneficial effect on USB and LVDS I/Os for instance, especially with the increasing impact of surrounding interconnects.
Encouraging co-development with partners has also reaped many benefits, speeding SoC design through combined efforts. Coupling Philips' low-voltage/low-leakage and non-volatile design competencies with externally developed compiler techno logy is a prime example. Linking extensive IP resources from both internal and external vendors to our strong reuse philosophy has relied on dedicated teams of localized and inter-site experts, working closely with early adopter and technology partners, and end-customers.
The professional capabilities of Philips Design Services have ensured various customer engagement models from pure turnkey, RTL hand-offs to jointly developed SoC ASIC and ASSP derivatives have been a success. In fact, this guaranteed access to a very broad knowledge base capable of solving virtually any problem in integrating all these technologies has been one of the key components in meeting CMOS12 design challenges.
Professional project management is an essential element of advanced SoC creation focused on rapid development and ease of procedure, it is also crucial for cost-effectiveness. Keeping exponentially increasing design dependencies on track, while targeting low-costs for end-customers, it is a absolute requirement in establishing a reputation for regular FTSS solutions. With manufacturing operations enabling very fast turn-around, designers can rely on short fabrication cycle times. Employing the facilities at the dedicated CMOS12 pilot line and utilizing Multi Project Wafers (MPWs) to minimize initial costs, has proven prototyping advanced complex SoC designs can still be fast and cost-effective.
The move to cost-effective next generation CMOS12 SoC system solutions requires the right blend of technologies, capabilities and expertise. Philips' commitment to driving forward CMOS process technology is satisfying many customers with advanced FTSS 0.12 µm solutions and is already preparing the way for 90 nm designs. The confidence to master the silicon run comes from the host of dedicated, skilled engineers and strong relationships that have been forged with partners and customers as they continue to ramp-up CMOS12 into volume production while taking the next leap in CMOS desi gn challenges.
Contributions from Philips' Chief Technology Office and Design Team project leaders were also included in this article.