Consumer demand for more functionality, higher performance and lower cost adds greater continual pressure on SoC manufacturers. Continuing advances in process technology, and the ability to design evermore-complex SoCs does not come without a cost. The next generation of processes brings about the next generation of challenges.
Today, simple physical models can no longer characterize CMOS technologies. Complex, second-order effects for new fine-line processes (resistance, inductance, crosstalk, leakage, and electromigration) are modeled mostly for the physical layer of abstraction. As a result, an additional number of design iterations may be required to fix problems found late in the design cycle.
The mask cost is increasingly becoming a roadblock when designing low to medium volume SoCs. The mask cost for such volumes represents a significant portion of the final chip cost. Even large volumes that are in the hundreds of thousands of units can suffer from high mask costs that reduce cost-effectiveness if frequent functional revisions are needed. For example, the mask cost in a 90-nm process technology is expected to be well over a million dollars, which is more than 2x the mask cost of 130-nm technology.
Due to rising time-to-market pressures, foundries are starting volume production on advanced process technology nodes before establishing the desired yield levels. As a result, yield is a critical factor in lowering costs and improving profitability. In addition, with the ever-growing trend of larger memory contribution to SoC content, the overall yield of an SoC design depends heavily on the memory yield. The natural step in further yield improvement is embedding fault-tolerant IP components. As a result, foundries recommend that if the chip has 2Mbits or more of memory, the memory needs built-in redundancy. By adding a redundancy scheme that enables the memory to self-test and self-repair itself, the overall die yield drast ically improves.
By integrating sophisticated digital cores with complex analog functions in single chip designs, SoC manufacturers are able to address the need for enhanced functionality and higher performance for market-leading applications in audio, video, multimedia, wireless, telecommunications, data communications, and a variety of other consumer applications. To further reduce system cost, more integration is required and additional components are added to the SoC puzzle; examples of such components are non-volatile memories, complex analog components and interfaces.
However, in building these complex devices, SoC manufacturers find themselves facing dramatically increased design and test complexity. Subsequently, the cost of test and test equipment for SoCs increases as well.
To meet these challenges, the next generation of SoCs require the next generation of silicon IP. In order to meet performance, power and cost criteria, using a one-size-fits-all approach is less than an optimal solution. In order to meet stringent needs of SoC design complexity, all the components have to be optimized to a particular design objective. Traditional components must be replaced with next generation components that will further reduce the cost of SoCs by simplifying testability issues, improving yield, and simplifying the design process. With the introduction of metal programmable cells1, designers can now not only reduce the cost of masks, but the turn-around time, as well as increase the predictability of first time design success.
Reducing NRE costs
Blocks of logic designed with metal programmable cell libraries can be functionally reprogrammed by changing only a few metal and via masks, thereby saving hundreds of thousands of dollars by preserving all other masks. Through careful planning, designers can significantly reduce overall non-recurring engineering (NRE) costs by sharing the cost of masks for a majority of metal layers between multiple des igns. It is not unusual that an installed EDA tool base is worth $100 million or more. Only high volume chips can justify this kind of investment. However, because the design flows and tools used with metal programmable cells are the same as standard cells, there is no need to invest in new EDA tools.
Designers can mix, on a block-by-block basis, standard cells and metal programmable cells on the same SoC. Depending on the available budget, a designer can trade-off area density for the cost of masks. On the 130-nm process, a user can expect routed density between 50K gates/mm2 to 130K gates/mm2 depending on the number of metal layers that are modified. In addition to saving on mask costs, designers can significantly reduce manufacturing time for design revisions. Take for example, the printer controller ASSP.
In order to keep the cost down, reducing the NRE cost is essential. In order to customize a controller for the particular printer, it is likely that the head controller and motor contro llers have to be modified. Also, frequent customization for image enhancements is needed. The cost of a full mask set, for a 130-nm process node, can exceed $500,000. Furthermore, it may take weeks to create all the masks. If metal programmable logic is used to design a block, modifying a limited amount of masks, for metal and vias, can customize a printer controller SoC. This approach results in multiple benefits:
- -Cost of masks will be shared between multiple designs. If the customization is done using three metal layers, incremental cost of masks per every new revision will be in the range of $100-120K.