SoC technical difficulties ahead; stand by
By Ron Wilson, EE Times
January 14, 2003 (1:48 p.m. EST)
Despite the assurances of foundries, ASIC vendors and tool suppliers that the problems with 130-nanometer CMOS are well in hand and that 90 nm is ready to use, there is a rumbling of voices from experienced design teams that not all is well.
Teams that have actually executed 150-nm and 130-nm designs say that there are in fact profound areas of concern with the technology. Some of those are static-problems that give you a "take it or leave it" choice. Some are much harder to pin down-problems that come and go, that may have been learning curve issues at a particular foundry or that require significant adjustment to the design flow but are not showstoppers.
Today's reality is that successful 130-nm designs are being completed, and chips are shipping in volume. But the successes have not been automatic. Successful designs have required new architectural approaches, new ways of employing intellectual property, new tool flows, significant a lterations to the design team or combinations of those measures.
In this week's In Focus, we offer reports from design teams and from tool, IP and process suppliers on what it takes to complete a successful 130-nm design. As always, while your experience may vary, these articles offer calibration points that a design team should examine when gearing up for a new design at 130 nm. And they offer a basis for extrapolation that senior management can use in preparing an organization for the even greater, and even less quantifiable, risks of 90 nm.
Several of the contributors advise that uncertainty in the 130-nm design process exists to such an extent that most teams would be well-advised to minimize it from the outset. From engineers at picoChip Designs Ltd. (Bath, U.K.), for example, comes a description of a system-on-chip (SoC) implemented as a highly regular array of processing elements. Discussed by Peter Claydon, fou nder and chief operating officer, t hat approach minimizes the team's need for outside IP, reduces detailed design to a handful of different blocks that can then be replicated, reduces the need for long routes and provides redundancy to fight the stealth monster of yield degradation. It's an impressive collection of benefits for a set of decisions made entirely at the architectural level.
A contribution from Uri Cummings, founder of Fulcrum Microsystems Inc., argues for a more radical architectural change: a wholesale shift from synchronous to asynchronous design to eliminate global-timing issues from the chip. Far from a graduate-thesis technology, Fulcrum designers claim, asynchronous techniques are ready for application. And they make the argument with a description of a completed chip that behaved as predicted.
An exclusive online contribution tackling interconnect issues head-on comes from Accelera Inc.'s Wolfgang Roethig. This article describes a design flow in which a new unified model library format permits delay, signal integrity, electromigration and process variation data to be included in a single library format. Thus, it permits detailed design tools to do simultaneous optimizations across myriad different but interrelated signal parameters, potentially eliminating the iterations that have led to schedule problems and failed projects on some recent designs.
Engineers from intellectual-property vendors MoSys Inc. and Virage Logic Inc.-both in the memory business-offer contributions on the significance of memory issues at 130 nm. Mark-Eric Jones, vice president for Intellectual Property at MoSys, and Brani Buric, senior director of product marketing at Virage Logic, both conclude that it is vital to the design team to have a wide range of memory types available in order to complete the design without debilitating side-effects.
And three SoC development partners have contributed as well. One hesitates to use the term ASIC vendor at this point, because, as these three ar ticles detail, the relationship between design team and chip development partner has become more complex than the traditional ASIC handoff would imply.
Philips Semiconductors' Thomas Beer- with input from design team project leaders-argues for the importance of a wide range of IP, from the level of basic libraries up through processors and huge functional blocks, all designed and verified in the process at hand.
In a similar vein, Dave Caffo, a top engineer with Texas Instruments Inc., gives a stark recitation of the problems that design teams are encountering: "Capacitive coupling creates signal integrity problems; gate oxide stress increases with coupled noise; and false switching opportunities are exacerbated by tight metal pitches, highly resistive wires and fast edge rates." He notes that "delay modulation from coupled noise has been evident largely as second-order for the past two generations but is now first-order." Among the other significant challenges: Power distribution and "gate, memory and I/O counts are introducing tool capacity and run-time issues and significant disk and CPU resource demands."
Caffo offers a list of the resources that TI, as an example, has brought to bear to see its clients through the process.
And in a note of at least equal importance but from an different point of view, a top manager at Toshiba warns that in today's designs much of the work is software, and that chip design teams that try to separate themselves from software issues do so at their own peril.
So there are the data points. Connect the dots, and you begin to see the real landscape of 130-nm design emerge. It's not a done deal, or an incremental extension of techniques that worked at 180 nm. Nor are all the problems solved, or even certainly solvable. But it's not an impossibility either.
Open eyes, strong partner and vendor relationships and massive doses of skepticism will be the old reliable tools that, in the end, prevail.