The Gatekeeper of a Successful Design is the Interconnect

By K Charles Janac, President and CEO, Arteris IP
EETimes (August 25, 2019)

An effective interconnect makes delivering a complex SoC easier, more predictable, and less costly.

Systems-on-chips (SoCs) are increasingly becoming networks to which you attach separate blocks of intellectual property (IP). SoC IP blocks include processors, memory controllers, specialized subsystems, and I/Os — and the blocks can be segregated from the interconnect IP to partition increasingly complex SoCs. Increasingly complex SoCs are required for a near future when electronics systems are allowed to make decisions.

An interconnect handles various types of traffic inside an SoC and is a mechanism for effective IP block integration. The interconnect is the most configurable IP in the SoC — typically changing many times during a project and nearly always changing between projects. It also plays a vital role in security and functional safety because it carries most of the SoC data and contains nearly all the SoC’s long wires and system-level services, including quality of service (QoS), visibility, physical awareness, and power management. The interconnect enables cache coherency in multiprocessor SoCs, high-performance and bandwidth levels in advanced driver assistance systems (ADAS) automotive chips and networking SoCs, and ultra-low power in long-running consumer devices.

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