By Manuel Mota, Sr. Product Marketing Manager, Staff, Synopsys
February 3, 2020
Higher data rates and more complex functionalities are increasing the SoC size for hyperscale data center, AI, and networking applications. As SoC sizes are approaching the reticle size, designers are forced to split the SoC into smaller dies to achieve high production yield and reduce overall cost. The die-to-die interconnect in such SoCs must not impact overall system performance and demand low-latency, power-efficiency, and high throughput. These requirements are driving the need for high-throughput die-to-die PHYs. Read this article to learn more about these requirements.
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System-on-Chip (SoC) designers for hyperscale data centers, artificial intelligence (AI), and networking applications are facing a challenge that has been trending since the advent of big data. Because of workload demands and the need to move data faster, such SoCs have become more complex with advanced functionalities and reached maximum reticle sizes. For this reason, designers are partitioning SoCs in smaller modules in a multi-chip module (MCM) packaging. These disaggregated chips require ultra- and extra-short reach links to enable inter-die connectivity with high data rates. In addition to bandwidth, the die-to-die connectivity must ensure reliable links with extremely low latency and power efficiency. This article describes several different use cases for die-to-die connectivity and essential considerations to make when searching for high-speed PHY IP for die-to-die connectivity.
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