Designing communications equipment in the 1990s was all about speed. Enterprises and service providers were struggling to keep up with the growth of the Internet, and equipment designers were innovating to build ever-faster equipment. That was evidenced by the shift from general-purpose processors, which were used in the earliest routers, to Layer 3 switching ASICs to perform the same routing function.
Today, as the Internet Protocol matures and finds new uses in service provider and enterprise networks, the design goals for networking equipment have shifted as well. Speed has been achieved; now enhanced services, system flexibility and control are the keys.
As security, quality of service and multimedia data streams become the new networking concerns, ASICs are being replaced by network processing chips (NPUs and high-speed multi-processor platforms), which offer performance and programmability. With these, network equipment desig ners can build new systems with the performance to provide deep packet inspection and the flexibility to change and adapt as new needs and standards become popular.
But beyond the trend toward programmable processor platforms, these network demands are sparking an evolution in board-level system interconnect. In an attempt to remove one of the last system-level bottlenecks, designers are migrating from bus-based to switch-based architectures. The System Packet Interface 4 phase 2 (SPI-4.2) implementation enables that migration, providing fast point-to-point interconnections between compatible devices. Additionally, with designs using SPI-4.2-based switched interconnections, designers gain improved board design reusability and field upgradability.
While much of the world has standardized on the Internet Protocol, network designers are using the standard in new and different ways. Voice-over-IP, for example, presents a demanding, real-time bit stream to a network technology that was designed t o provide best-effort responsiveness. Another trend is specialization to add functionality to IP, ranging from application-specific networks, such as storage-area networks (SANs), to specialized equipment like firewalls and content servers. With the increasing dependence on the network, system architects continue to require increased control of the network.
With sophisticated data security systems and user policies, network managers are demanding more advanced bit-stream processing for remote management, quality-of-service, firewall and virtual-private-network security. Generally, such functions are introduced in separate standalone systems but, over time, are incorporated into more mainstream networking hardware.
To provide the foundation for the new network functionality, chip vendors are increasingly backing SPI-4.2 as a versatile general-purpose board-level silicon interconnect standard. SPI-4.2 is a 10-Gbit/second system interconnect implementation agreement drafted by the Optical Inter networking Forum (OIF) for connecting link-layer and physical-layer devices on board in Gigabit Ethernet, OC-192 asynchronous transfer mode or Sonet/Synchronous Digital Hierarchy applications. SPI-4.2 is a parallel interface, breaking down throughput into 16 independent streams, each transmitting data at rates up to 622 Mbits/s. It is designed for the efficient transfer of both variably sized packets and fixed-size cells.
The OIF standard for SPI-4.2 specifies a point-to-point protocol with 16-bit transmit and receive data paths and support for 256 channels (referred to as ports in the specification), which gives it the port granularity to support the full range of Sonet/SDH and Ethernet applications.
The standard separates the synchronous PHY layer from the asynchronous packet-based processing performed by the higher layers of the OSI protocol stack. That allows the transmit and receive data transfers to have clock rates independent of the actual line bit rate. P>
Additionally, the FIFO status information is sent separately from the corresponding data path on both transmit and receive interfaces. With out-of-band FIFO status information, it is possible to decouple the transmit and receive interfaces so that each operates independently, making SPI-4.2 suitable for both bidirectional and unidirectional link layer devices.
All of this results in an efficient, high-speed point-to-point interconnect solution. Because of its simplicity and high speed, SPI-4.2 is being adopted for a variety of applications beyond its original intent. For example, in storage-area networking, storage-processing silicon is connected to Fibre Channel interface silicon using SPI-4.2.
With SPI-4.2 as the interconnect solution, designers can adapt their interconnect architecture away from a bus-based design (or discrete daisy chain of chips) to a higher-speed, more-programmable switch-based architecture. A switch-based interconnect is configurable, so a designer can re-purpos e one of the devices on a board simply by reconfiguring the data flow through the switch. There's no need to respin the board layout. Thus, the network designer can make more efficient use of the programmability power of today's NPUs, multiprocessor platforms and related application-specific standard products (ASSPs).
Today, this is accomplished through intelligent SPI-4.2 port mapping. In the future, dynamic SPI-4.2 frame routing will displace the initial, static implementation. The Network Processing Forum has published a specification, called the Streaming Interface (NPSI) Implementation Agreement, that leverages SPI-4.2 for dynamically interconnecting multiple silicon devices (including framers, NPUs, coprocessors and switch fabrics) at 10-Gbit line rates. Multivendor adoption of the agreement will accelerate the migration to switched architectures.
Switched interconnection can lead to a more efficient use of expensive silicon resources in a system. In one example, a design uses a discre te daisy chain to connect the I/O with an NPU, a traffic manager and the switch fabric interface on the ingress data path. On the egress data path, the fabric interface chip communicates with another NPU, which processes the data and forwards it to the I/O chip. Both of the NPUs perform the same function, but because of the discrete daisy chain, both must be used.
Replace that bus with a switch interconnect that is connected to the I/O, the traffic manager, the NPU and the fabric interface, and new possibilities arise. Because both the ingress and the egress data paths flow through the switch, the design becomes simpler. Only one NPU is needed because it can be accessed by data on both paths. Similarly, leveraging multiple SPI-4 ports per device, the traffic manager can process data on both data paths.
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