English
Simplifying AC and DC data acquisition signal chains
By Wasim Shaikh, Srikanth Nittala (Analog Devices)
embedded.com (August 12, 2020)
Sampling phenomena in analog-to-digital converters (ADCs) induce the problems of aliasing and capacitive kickback, and to solve these problems, designers use filters and driving amplifiers that introduce their own sets of challenges. This makes achieving precision dc and ac performance in medium bandwidth application areas a challenge and designers end up trading off system goals to do so.
This article describes continuous-time sigma-delta (∑-Δ) ADCs that inherently and dramatically solve the sampling problems by simplifying signal chains. They remove the need for antialiasing filters and buffers, and solve signal chain offset errors and drift issues associated with the additional components. These benefits shrink the solution size, ease solution design, and improve the phase matching and overall latency of the system. This article also draws a comparison with discrete-time converters and highlights system benefits, as well as the constraints of using continuous-time sigma-delta ADCs.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
Related Articles
- Designing AC/DC Adaptors for USB Type-C Power
- Design trade-offs of using SAR and Sigma Delta Converters for Multiplexed Data Acquisition Systems
- Data acquisition systems and SoCs - A guide
- Mixed-Signal Designs: The benefits of digital control of analog signal chains
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
New Articles
- From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
- Embracing a More Secure Era with TLS 1.3
- New PCIe Gen6 CXL3.0 retimer: a small chip for big next-gen AI
- Maximizing ESD protection for automotive Ethernet applications