EETimes (August 24, 2020)
There is a transformation occurring in high-end embedded applications as processing spreads from the cloud to the edge and the end points of the Internet. Performance requirements are increasing rapidly and changing the architecture of processors and how they are implemented in designs. This is behind the increased use of multicore processors to deliver higher performance. Most high-end processors today are available with support for dual- and quad-core configurations. There are a few that support up to eight CPU cores, but even this won’t deliver the performance needed for emerging applications in storage, automotive, networking, and 5G. Next-generation embedded applications need scalable support for larger CPU clusters and specialized hardware accelerators to deliver the required performance. Large multicore processors will require a new architectural approach to enable higher performance and not create additional implementation and timing closure problems for embedded designers.
Embedded Performance Challenges
It is no secret that advanced process nodes no longer deliver the higher clock speeds and lower power consumption that they once did. For many process generations logic speeds have continued to increase but memory access times have not (Figure 1). The speed-limiting paths in processors are almost always through memory. This is a situation that is not likely to change for future process nodes because of the very real limitations of semiconductor physics.
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