Burning rubber on the SoC freeway
Burning rubber on the SoC freeway
By Nicolas Mokhoff, EE Times
February 11, 2003 (2:56 p.m. EST)
Trading off performance for power has never been an easy task. This week we'll take a look at how some developers are managing to juggle the gigahertz-performance requirements of today's huge system-on-chip designs and the demands those systems make on power consumption.
A report from the trenches at the International Solid State Circuits Conference, held this week in San Francisco, is followed by several contributions from experts that shed light on various aspects of SoC design and the tools needed to make the appropriate design tradeoffs in getting SoCs out the door. At GHz speeds, burning rubber will only wear out the SoC wheels of that racing car under your design hood.
In his article, Lyle Adams, vice president of engineering at Palmchip Corp.,explains how, as chips get larger and faster, some features of networks are advantageous to incorporate into chip designs. These include a network topology, latency tolerance and error detect ion. Due to the fact that tomorrow's gigahertz chips will be more complex and because of the additition of on-chip networking features, error detection and handling will have to become an integral part of the chip design. And, power consumption will become the barometer for the pace of integation.
Raminderpal Singh, technical manager at IBM's Analog Mixed-Signal Foundry and co-chair of the Analog-Mixed-Signal working group at VSIA (http://vsi.org) claims that today's design methodologies allow us to build anything fast from GHz microprocessors to multi-GHz RF cores. At the same time, we are able to build huge 100M transistor IC's, with a multitude of IP blocks. But Singh suggests that the problem comes in building 100M transistor designs with multi-GHz processor cores and GHz+ chip-wide buses, specifically when IP blocks are being imported from many different sources/companies.
This problem is comparable to the difficulties faced in analog IP integration in SoC designs, but has the added co mplexity of chip-level high-speed performance. In his article, he steps through the issues faced while focusing on the key challenges.
In order to minimize the impact on SoC power consumption, a new integration strategy is necessary in the era of GHz performance, according to contributor Bill Krenik, wireless advanced architecture manager at Texas Instruments. His strategy integrates, in CMOS silicon, all of the activities needed by a particular function.
For example, a complete quad-band GPRS transceiver, including all baseband analog and RF functions, may be integrated into a single chip. A GSM module contains all of the radio, logic, A/D and D/A converters and so on needed for GSM operation. Similarly, Bluetooth, WLAN, and GPS are also supported with their own single chip solutions. Because they are tiny and wireless, a careful watch over the design process is paramount especially in order to avoid any possible anomalies that would raise power consumption above acceptable levels.
In his contribution, Dave Reed, vice president of marketing at Monterey Design Systems, discusses two complementary approaches to limiting leakage current. The static approach is design independent and may be implemented with multiple threshold (Vt) libraries and design tools that support these libraries. The dynamic approach requires that the chip designer employ techniques during the design process, to dynamically deactivate parts of the chip during periods of inactivity, and is thus design dependent.
Reed focuses on the static approach of SoC designs in his article and shows how a combination of multiple Vt libraries and advanced physical synthesis technology can effectively reduce leakage by as much as 30 percent on a 130nm design.
In order to help SoC designers fight the ever-increasing GHz creep, and thereby the ever-increasing power challenge, Pradeep Fernandes, vice president of product engineering at Get2Chip Inc., offers a global optimization strategy that takes a global v iew not only of the design - all of its constituent elements - but the design process itself.
Design, verification, implementation, optimization and test must be viewed alongside the master plan for the entire device. He says that this may sound trite, but this global view is painfully absent in many projects. Far from a master plan, the mode of operation is often to react to problems as they arise.
And, simply from a speculative view on reaching 1 GHz designs using IP blocks, Ed Smith, vice president of sales and marketing at fabless ASIC startup Telairity Semiconductor, explains the need to create a wide selection of hardened building blocks with a sufficiently small granularity to ensure that most digital functions are constructed, but are still architecturally large enough to enable the elimination of performance issues. He offers specifics on a speed-optimized, hardened IP as an example.
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