Interest in analog IP outpaces execution

Interest in analog IP outpaces execution
By Stephan Ohr, EE Times
February 12, 2003 (4:31 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030211S0038

SAN FRANCISCO — Can analog intellectual property (IP) be traded the same as digital IP? "It won't be heaven — but what is heaven anyway?" said Bill Redman-White, a technology fellow at Philips Semiconductors, who summed up the sentiments of panelists wrestling with the question at the 50th International Solid-State Circuits Conference.

"We can reuse analog and RF designs within a company," Redman-White said. "IP trade exists, though it's not a supermarket."

The digital IP market is growing 25 percent per year, and is expected to reach $1 billion this year, according to Gartner Dataquest. But engineers with analog design skills are not increasing as rapidly as the number of ICs utilizing analog, RF and mixed-signal components, said Rudy Koch, RF and mixed-signal design chief at Infineon Technologies (Munich, Germany), who organized the ISSCC session titled "Analog IP — Stairway to SoC Heaven?" Koch asked if analog IP could fill the gap. Panelists and audience members were considerably more optimistic than those at a similar panel held last June at the Design Automation Conference.

"It's wishful thinking to believe analog IPs should traded like digital when, in fact, it doesn't need to be," Redman-White concluded. But it can be traded, he said. "The devil is in the details."

And the details are nasty. Unlike digital IP blocks that can be completely specified by propagation delay and fan-out, analog blocks are defined by dozens of key parameters, said Masao Hotta, chief engineer and general manager of the mixed-signal design group at Hitachi Ltd. (Gunma-Ken, Japan). While Hitachi's most advanced system-on-chip (SoC) designs are constructed in 0.18-micron CMOS, the A/D and D/A blocks most frequently reused are in 0.35-micron geometries.

Analog blocks must account for slew rate, gain, bandwidth, noise and distortion, Hotta explained. In an SoC, the y are sensitive to layout, device matching, symmetry, thermal gradients, signal swings, zero levels and proximity to switching circuits. With so many potential stumbling blocks, Hotta asked if the IP user or provider takes responsibility for insuring the circuit block works properly within an SoC. The safest course, he concluded, was to trade properties only in the same process and for the same specific applications.

Phillippe Magarshack, vice president for R&D at STMicroelectronics in Crolles, France, confirmed Hotta's worries that analog blocks are often "polluted" by their proximity to noisy digital circuits. He characterized analog IP as a "necessary evil," since so many modern ICs depend on phase-locked loops (PLLs) and companies are frequently forced to go outside to acquire them.

Magarshack noted a stratification among IP and the tool vendors capable of supporting them. Identifying low-frequency, medium-performance devices like op amps, PLLs and low-resolution data converters as "commodi ty IP," and RF low-noise amplifiers and other items requiring a higher skill set for utilization as "star IP," Magarshack said that a commodity analog IP trade held the most promise.

Troublesome artists

The trouble with analog designers, said panelist Georges Gielen, a professor at Katholieke Universiteit (Leuven, Belgium), is that they think of themselves as "artists." Hand-tweaking every transistor, their productivity is about one device per hour. Time-to-market — a key concern for commercial ASIC suppliers — can be improved if the productivity of IC designers could be increased with decent CAD tools, said Gielen, who serves as a technical advisor to analog tool startup Analog Design Automation. Automatic synthesis tools could generate soft IP, while resizing and automated layout tools could form analog IP blocks, Gielen said.

This paved the way for Thomas Heydler, president and chief executive officer of tool vendor Barcelona Design (Newark, Calif.), who said his company 's tool set synthesizes analog IP. The geometric programming algorithm, capable of resolving a 120,000 x 120,000 variable matrix, makes it easy to model complex circuits and fabrication processes, and generate soft IP, Heydler said. Such processing power cuts design time by placing virtual silicon IP quickly in the hands of a novice designer, he said.

Telling response

Audience reactions to the panel were most telling. "Anyone can hand you a 'black box' and tell you that's a folded cascode amplifier," complained Allen Sullivan, a design engineer with Microchip Technology Inc. (Chandler, Ariz.). "Analog IP is useless to me unless you can give me the test suites, the means of validating this design."

His concerns prompted a question from the podium, and a fairly dramatic audience response. Was analog IP a theoretical possibility, or was it becoming a dire necessity? "Assuming you could get what you want," the audience was asked, "how many of you would actually buy an analog IP?"

The audience response was tentative at first, and then clear and unmistakable: a sea of hands were raised. Roughly 200 respondents, two-thirds of the audience, said they would purchase analog IP.