SoCs are 'dead,' Intel manager declares
SoCs are 'dead,' Intel manager declares
By David Lammers, EE Times
February 12, 2003 (4:26 p.m. EST)
SAN FRANCISCO The system-on-chip movement is "dead," ambushed by the cost of additional mask layers needed to marry digital logic with memory and analog functions, Intel Corp. architecture manager Jay Heeb told the International Solid-State Circuits Conference on Tuesday (Feb. 11). Rather than SoCs, the chip industry will move instead to 3-D devices distantly related to today's stacked packages, he said.
Heeb, who manages Intel's Xscale processor core design effort in Chandler, Ariz., made his comments at an ISSCC session on the future of integrated circuits for 3G mobile phones. "The SoC is dead because of too many mask layers," he said. "We need to be bolting the optimum technologies together in what I call a So3D, a system-in-3D package. Then we can tune an application to a specific, optimum substrate."
Allowing that he hesitated to use the word "package" (because 3-D integration is much more than that), Heeb said he prefers to call semiconductor die "pass through elements" that would be linked by "molecular velcro, or capacitive coupling."
Heeb acknowledged that Intel's current cellular phone chips include on-chip flash memory, which require additional mask layers. While that device is appropriate for today's wireless phone market, he said the 3G phones that come to market in 2010 will be much more memory-intensive and will require a different approach.
By the end of the decade, 3G wireless phones will be activated by speech input, and much of the information flowing into the handset will be visual, he said. Both speech and video are "very memory-intensive, which means that as much as 90 percent [of the transistors in a cell phone's chip set] will be non-volatile memory. Rather than integrate that onto a single die, you want to be able to ride non-volatile scaling and add that to the system with 3-D integration techniques," Heeb said.
Companies ranging from IBM Microelectronics to startup Ziptronix Inc. have detailed methods recently that place bare die in close proximity to link the on-chip interconnects of digital, analog, MEMS and optoelectronic devices.
"These could interconnect exactly as if they were a singular chip, and the architecture would map system elements to the appropriate device," Heeb said.
He then detailed the changes to today's design requirements needed to integrate 3D-type devices. "The package becomes, up front, part of the architecture," he said. "It would require 3-D floor planning, routing, estimation and extraction tools, 3-D debug, and FIB [focused ion beam] for design and repair."
Avner Goren, a senior planning manager from Texas Instruments Inc.'s wireless IC operation, sharply disagreed with Heeb's view.
TI has created SoC devices that sweep analog functions onto a single digital CMOS die, sharply reducing component count for a design, including the number of passives.
"We've done it" for Bluetooth, Goren said, and will do the same for the cellular handset market. TI's design teams are merging the baseband function with a digital radio and integrated power management function for GSM phones. That main digital CMOS device will be stacked with memory devices in a single package, he said.
"Next year we will be in a single chip that is all CMOS. Only the power amplifier and about 25 passives will be off-chip. It is doable and it will happen," Goren said.
TI will apply design reuse techniques to extend the single-chip concept, enabling new silicon spins to meet the needs of specific customers.
"For SoCs we are moving from cells, to blocks, to integrating whole IP [intellectual property] cores. We believe that it is an interconnect-centric approach that is flexible," Goren said. "At TI we have developed OCP, or open core protocol, in which the interconnect is decoupled from the logic by the OCP. We believe this is flexible enough to meet the changing needs of the market."
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