Chip Design Engineers are on a binge today, drawing up design plans for unprecedented, ever-increasing functionality on a single chip. Many times this surge encounters a brick wall in the form of prohibitive test development and production test costs. Thankfully, Design-For-Test tool vendors are providing multiple innovative solutions for reducing such test costs substantially. Multiple solution options always pose tough choices for the design and test teams.
Today there are two major options to choose from when confronted with test cost reduction problem. One is generation of extremely compact test patterns and the other is to incorporate test generation and response-capture circuitry on the chip. This article discusses both approaches, including their merits as well as specific considerations that must be taken into account. A summary table is provided to compare both approaches.
Climbing to the top
There's an effort to climbing any mountain, but once at the top, the exhilaration and the views and the achievement make the effort worthwhile. Putting logic BIST, or self testing, into a chip is a lot like that -- there's an effort involved, and extra circuitry on the chip, but once you've decided to do it, once it's there, the benefits are enormous. In fact, logic BIST is the Mt. Everest of test solutions-you can climb no higher.
There is an alternative to logic BIST -- use scan circuitry on the chip and apply compacted ATPG vectors, or test patterns. But that's a lot like staying at the bottom of the hill and only looking at pictures of the views from the top. Let's take a look at both techniques.
Logic BIST requires some extra circuitry and, because it is based on a final signature, carries rules that must be followed. In other words, logic BIST compels you to clean up your design (which, of course, ought to be standard procedure, anyway) to avoid unknown states, or values, that might throw off the signature (X-bounding). The alt ernative is that you may have to add circuitry to mask off such states. The end result is a better chip, and a better board later, because erroneous inputs will be detectable at both stages.
By contrast, ATPG vectors, or patterns, that create unknown states on any one or more scan flip-flops can basically be handled as "ignore" states that are masked off at the tester. At worst, such "ignore" states forces generation of more ATPG patterns to detect faults that could be detected earlier, thus extending the time needed to test the chip.
But logic BIST is the better solution overall because it requires no interaction with a large, expensive external test systems. The testing is all built-in, and only a small low-cost tester is needed to "launch" the test. Test costs are slashed dramatically. And, of course, the BIST is there for use down the line, at the board-level, subsystem-level, system-level testing stages. This is what makes it also suitable for field and non-invasive testing of crucial electron ic equipment
So why all the activity in compressing test vectors? In reality, ATE may still be necessary for analog and other production testing (stress, continuity, and so on). If scan and ATPG are the choice, then the goal is to use as few vectors as possible to cut the test time. The table below summarizes the basic differences between the logic BIST and scan/ATPG compaction approaches:
Figure 1 -- Logic BIST versus scan/ATPG
Moving down the features list, you clearly can see the overall test cost advantage of the Logic BIST solution in terms of using smaller ATE, test data volume reduction and test time reduction. Further, error masking is non-existent or, at best, difficult on an external tester, while it is inherent in true BIST. With the external approach, you've got to mess with error masking on your own.
Second, "at-speed test," the ability to run vectors at the rated top functional speed of the chip under test -- a crucial capability for today's timing-sensitive chips -- is also inherent in true BIST.
But at-speed is a near impossibility for external ATE running highly compacted vectors because today's chip clock rates outpace those of most testers. That means you cannot readily detect delay faults -- score another one for true BIST -- because the too-slow external machine applying the vectors struggles to keep up.
Logic BIST wins out in the diagnostics arena, too, because, by its very methodology, the resultant signature is predictable. That is, the pseudo-random nature of the pattern generation and the fixed signature-conversion circuitry team up to produce a predictable end result. With compacted scan, node faults are detected by observation at external pins; however, the causes of the faults are not easily pinned down because, typically, a huge set of patterns must be mapped into a highly compressed set, which then must be unmapped for the purposes of diagnostics. That is not an easy process, and it is c ertainly time consuming.
The upshot: True logic BIST can slash test time up to a hundred-fold, whereas with the scan/ATPG-compaction method one would be lucky to get a 20 times reduction. For the sake of accuracy, it's true that the pseudo-random approach may require more patterns. However, because the patterns are applied full speed, testing still takes less time than the ATPG approach.
BIST, with its on-chip pattern generation, also drastically cuts the amount of test data, so much so that, as explained in the table, the word "Infinite" is apt to describe the data volume reduction. Whatever the descriptor, Logic BIST is a clear winner in this department.
Which brings us to design changes. This is a no-brainer. With BIST, a designer just makes the required changes and re-runs the random patterns. The result is a new signature, different from the previous one. With the other approach, expect to spend lots of time in setting up, rerunning ATPG, re-simulating for fault coverage and re-mapping a new set of patterns. Come another ECO, and you must start the ATPG run all over again.
The benefits of logic BIST are so great that at least one major vendor tries to disguise its scan/ATPG compression product as a form of logic BIST. A little comparison shows that the vendor doesn't quite make the "grade," because an external stimulus generator, with its attendant cost, is still required in the their technique. Using the word "BIST" to hide what is really a scan-based, ATE driven, hybrid solution muddles the market.
On a final note, it's acknowledged that the increase in area impact is often the designer's reason for turning to "compact" ATPG, despite all the advantages of logic BIST. But look at the hybrid approach. Regardless of what the vendor may say, the scan chains and other circuitry may claim every bit of the same area as true BIST. Remember, when it comes to test, you can't beat the view from the top. It's where the real money savings hang out.
Ravi Apte is vice president, strategy and business development, at
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