Lower Process Nodes Drive Timing Signoff Software Evolution
As process nodes have continued to shrink down to 5 nm and below, there have been steadily fewer semiconductor fabrication facilities that have been able to produce semiconductors at each subsequent node. Now, there are only a handful of semiconductor companies able to produce 10-nm, 7-nm, and 5-nm devices. Though there is substantial capital and other resources necessary to build facilities that can produce devices at these smaller nodes, one of the largest drawbacks is being able to reduce variability of the process to a low-enough threshold that acceptable yields are achievable.
Current semiconductor manufacturing technology is pushed to its limits to meet lower node requirements, and variabilities that were previously of a low-enough impact to be disregarded are now posing design and fabrication challenges. As simulation software is based on the assumption that certain variabilities can be accounted for and their impact mitigated at the design stage, timing analysis and other semiconductor design software is now challenged with mitigating the latest variabilities in addition to all past variabilities.
Addressing these new challenges results in timing analysis that must now reach even greater levels of accuracy over a much larger set of corners that was needed at previous nodes.
Moreover, there is a need for timing analysis tools to become much more physically aware and produce greater productivity while also minimizing computing resources requirements and maintain manageable run times on reasonable numbers of computing cores and memory.
This article aims to inform readers on key aspects of achieving the necessary levels of accuracy, performance, and productivity with timing analysis software and innovations with timing analysis that are enabling chipmakers to take advantage of the latest process nodes.
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