English
MIPI CSI DSI C-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
Multi-Layer Deep Data Performance Monitoring and Optimization
By proteanTecs, Siemens Digital Industries Software
Combining functional and parametric monitoring of the real-world behavior of complex SoCs provides a powerful new approach that facilitates performance optimization during development and in the field, improves security and safety, and enables predictive maintenance to prevent field failures. proteanTecs’ Universal Chip Telemetry (UCT) and Siemens’ Tessent Embedded Analytics are complementary technologies that enable just such an approach, informed by Deep Data.
Examples based on ADAS and autonomous driving systems demonstrate how the two systems interact to shine a light on even the most complex problems in electronics design, production and deployment.
|
E-mail This Article | 
|
|
Printer-Friendly Page |
|
||||||
Related Articles
- Performance optimization using smart memory controllers, Part 1
- Optimizing embedded software for power efficiency: Part 3 - Optimizing data flow and memory
- Optimizing High Performance CPUs, GPUs and DSPs? Use logic and memory IP - Part II
- Optimizing performance, power, and area in SoC designs using MIPS multi-threaded processors
- System Performance Analysis and Software Optimization Using a TLM Virtual Platform
New Articles
- Is your career at RISK without RISC-V?
- Radiation Tolerance is not just for Rocket Scientists: Mitigating Digital Logic Soft Errors in the Terrestrial Environment
- Weighing Chip-Design-Verification Challenges for MedTech
- Using edge AI processors to boost embedded AI performance
- How Low Can You Go? Pushing the Limits of Transistors - Deep Low Voltage Enablement of Embedded Memories and Logic Libraries to Achieve Extreme Low Power