SAN JOSE, Calif. The SystemVerilog 3.1 specification is undergoing final reviews and Synopsys plans to have a synthesis tool for SystemVerilog assertions in the next 12 months, said Synopsys CEO Aart de Geus. The move is intended to solidify SystemVerilog as the next significant productivity booster for chip design, he said in a Monday (Feb. 24) DVCon keynote speech, "Design For Verification: a new paradigm."
De Geus described how the uncertain socioeconomic climate, growing design complexity, and manufacturing costs are combining to prolong the semiconductor slump. On top of this, the ongoing design gap between what can be designed and what can be verified in a reasonable amount of time is again beginning to widen. However, de Geus said the EDA industry is apparently on the verge of again closing the design gap, thanks largely to standards body Accellera's SystemVerilog language, which is expected to be approved and rolled out a t the Design Automation Conference in June.
"If you look back at the last 15 years, it has really been the age of simulation, with companies owning enormous server farms," said De Geus. "I believe we now have the opportunity to start the "design for verification" age.
De Geus said that in the mid-1980s, the chip design industry saw a huge design gap emerging as the result of new process geometries and gate counts. The industry at the time had two competing verification languages, Verilog and VHDL. The languages however did not help close the design gap until logic synthesis became a commercial entity.
Indeed, Synopsys succeeded in taking a subset of the Verilog language, and with its tool Design Compiler optimized it for design and in turn easier verification, thus closing the gap.
In that time however, the industry was divided into the Verilog and VHDL camps, which slowed the design industry's progress toward closing the design gap.
De Geus noted that today's gap can be closed more rap idly because the design industry seems to be backing one language SystemVerilog, which uses contributions made by Co-Design Automation, a company Synopsys purchased last year. Synopsys also has a hand in SystemVerlog's main competition SystemC, but de Geus noted that will be used for an even higher level. SystemVerilog is an incremental step and will not require designers to make a drastic change or learn an entirely new language.
SystemVerilog 3.1 claims to bring design and verification to the assertion level, above today's Verilog and VHDL. The language, which has system level language attributes of C++ added to Verilog, allows engineers to describe a design in terms of intent or assertions. These assertions can be used by not only simulators but test bench generation and formal verification tools.
"The conciseness of the SystemVerilog language is of enormous value, said de Geus, pointing to a slide comparing a page of Verilog code written in three paragraphs in SystemVerlog. "This is a signi ficant way of reducing the number of lines of code that need to be written."
De Geus noted that simulation and test bench generation can also run from a single executable, which promises to cut overall simulation run times.
However, as a panelist in a later DVCon session said, the language will really not be useful and have an impact until there is synthesis tool for it.
The language has yet to be fully approved by Accellera and is expected to be release at DAC in June. A potential assertion synthesis tool vendor would then have to outline a synthesizable subset of the language so that it can be used effectively and efficiently in the design process and translated to RTL and via legacy tools down to gates.
De Geus told EE Times that a commercial offering from Synopsys will likely be release in 12 months. A source familiar with the inner workings of Synopsys said the company could, if it pushed the schedule, have something ready by DAC.