By Bipul Talukdar, SmartDV
A well-repeated truism throughout the semiconductor industry is that chip design verification is complex and often takes up the largest portion of a design project’s schedule –– sometimes as much as 70% –– and an ongoing challenge facing verification engineers. The all-important methodology is used throughout the chip design process and considered the gatekeeper at each stage of the process as the design transitions from a high-level description to detailed layout of the chip and ultimately to first silicon prototypes.
The last hurdle of any project before committing to volume manufacturing requires verifying the prototype silicon device or an FPGA programmed with the final design. It’s a crucial test to confirm the device meets all specifications for functionality and performance. Once the specifications are validated, the final system is released to production. Traditionally, a custom hardware and software setup is created to perform this critical final validation.
FPGA prototyping and hardware emulators are commonly used in the verification process. A similar approach to FPGA prototyping is adding post-silicon verification IP (PSVIP) to test prototype silicon. The verification IP component is supplied in synthesizable register-transfer–level code programmed into an FPGA. The FPGA is then hardwired to either the prototype silicon device under test (DUT) or to another FPGA containing the DUT, an approach often used prior to silicon prototypes as a final check before committing to first silicon.
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