Transaction-level models eyed as SoC enabler

The panelists tossed around such questions as whether the transaction level (TL) is truly useful for the design or verification of SoCs; how TL might speed t he design process and lower the risk of deign failures; and the implications of the tools, languages and intellectual property (IP) used in the design/verification process.

'Crisis of complexity'

Gartner Dataquest analyst Gary Smith voiced the panel's concern about the problems of complex SoC design, saying that for the first time in the semiconductor industry, designs are not using at least 50 percent of the silicon area available to them. "This crisis of complexity needs to have the design industry move to the next level of producing third-generation tools," he said. "Are TL-based tools the answer?"

The problem is the lack of a good definition of transaction-based modeling, said panelist Dan Gajski, a University of California, Irvine, professor. "Everybody has their own idea of TLM, and one EDA vendor's idea is not in synch with another's."

"We need to formalize the abstraction level of system designs," said Donatella Sciuto, a professor at the Politecnico di Milano in Ital y. "There are requirements for a single API [application programming interface] for IP cores, common semantics for the EDA vendors and acceptance by IP vendors of those semantics."

"It's all about context," said Chris Leonard, SLD methodologies manager at ARM Ltd. "A model used in the wrong context gives wrong results." While the industry has a handle on clocked domains at the RTL and transfer layers as well as at the unclocked domains of the protocol and message layers, Leonard said, it's the boundary area between event transaction and a clock edge's parameters that needs research.

"It's important to know at what abstraction level to model," said Frank Ghenassia of STMicroelectronics' Crolles Research Center (Grenoble, France). At ST, he said, four designs that used TLM methodologies are already out the door, and six more are ready to be implemented.

TLM is too fuzzy to define, said Stuart Swan, senior architect at Cadence Design Systems Inc. He suggested that designers use function calls to model communications between hardware and software modules as a start.

"TLM applies to both design and testbenches," said Swan, declaring that TLM is already part of such verification entities as the Vera language and the tools from Verisity. The system-level methodology will take longer to entrench itself in design, he said, but many companies, including Cadence, are working to develop TLM flows today. "There may be an issue with the designer skill set to use TLM at the appropriate abstraction level," said Swan.

"The TLM techniques are not new," said Joachim Kunkel, vice president of marketing at Synopsys Inc. "The network crowd has used TLM for a very long time." Kunkel said the size of today's SoCs is forcing designers to look at TLM as a design methodology. He hinted that announcements at the Design Automation Conference in June will tell how to go from TLM to RTL.

Ultimately, "semantics matters," said Gajski of UC Irvine. "It's not important so much what language you use to define your models. But you'd better develop them so that all understand what you mean and all can use that knowledge to develop their own models."

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