Nonvolatile memories for 90nm SoC and beyond
Nonvolatile memories for 90nm SoC and beyond
By Erwin J. Prinz, Memory Device Engineering Section Manager CMOS Platform Device Development, Digital DNA Laboratories, Motorola Semiconductor Products Sector, Austin, Texas, EE Times
March 18, 2003 (1:04 p.m. EST)
In many SoC applications, it is desirable to store code and data in a non-volatile memory to maintain the state of the system even in the power-off state. The most flexible solution is to embed a Flash EEPROM into the SoC, in which small blocks of non-volatile memory (NVM) can be erased and re-written if a change to the data or code is required. This also enables in-system programming of the SoC. Examples of a state-of-the-art SoC's include microcontrollers for engine control, which contain a CPU, cache SRAM, numerous peripherals to connect to sensors and actuators, and Flash EEPROM for non-volatile code and data storage. To achieve non-volatility in a SoC, the CMOS logic baseline process is modified to include the process steps necessary to fabricate the Flash EEPROM bitcell and the supporting devices such as peripheral high voltage transistors. The art of embedded NVM design is to strike a balance between customer feature requirements, manufacturab ility, and reliability.
Embedded NVM technology typically lags baseline logic productization by one to a few years. Currently, the sweet spots for 8, 16, and 32-bit microcontrollers are 0.5-0.25 micron, 0.25-0.18 micron, and 0.25-0.13 micron technology nodes, respectively.
In most embedded NVM's, information is stored as charge on a "floating gate" which is completely surrounded by insulators, and which affects the threshold voltage of a transistor such that one bit of information corresponds to its on- and off-state. Charge is moved into and out of the floating gate by physical mechanisms such as hot-carrier injection or tunneling. Either method requires voltages higher than the core supply voltage. Typically a potential of ±9 volts is required. To support these elevated voltages, peripheral transistors are built with thicker-than-nominal gate oxides, and charge pump circuits are employed to generate high voltages from the chip supply voltage. For more advanced technology nodes, the disparity between peripheral and core supply voltages increase, resulting in large peripheral overhead which translates into module area and added die cost. Especially if fast read access is required, the peripheral overhead can dominate the NVM module area due to the poor transconductance of the thick oxide transistors. Since in the SoC the Flash EEPROM bitcells occupy only a fraction of the total die area, minimizing bitcell size at the expense of process complexity is not as important as in stand-alone high-density Flash EEPROM. Instead, it is more desirable to trade bitcell size for low peripheral voltages. Therefore, bitcells containing more than one transistor are sometimes applied.
With advances in manufacturing technology, Flash EEPROM bitcells have been scaled down to smaller feature sizes, both photolithographic dimensions and the thicknesses of the insulators surrounding the floating gates. It has been found that there is a scaling limit for the insulator through which the charge is transported dur ing the write and erase operations at high voltages. To maintain high reliability for safety-critical applications, the insulators surrounding the floating gate must be thicker than 100 angstroms if error correction is not employed. This is due to the fact that a single point defect in an insulator is sufficient to create a leakage path through which the entire floating gate charge can leak out. Based on today's understanding of device physics, it is believed that floating gate based embedded NVM can be scaled until at least the 90nm technology node, with bitcell sizes of 0.08-0.12 square microns and a maximum write/erase voltage of ±9V. The fraction of area spent on peripheral transistors will increase significantly with each technology generation.
To address the scaling limitation of the insulators surrounding the floating gate, "thin film storage" (TFS) memories have been developed. Instead of using floating gates, charges are stored in a thin insu lating film which contains storage sites such as traps or small silicon crystals. The charges cannot move easily from site to site, and therefore a single oxide defect does not lead to complete charge loss. Therefore, improved reliability is expected for thin film storage compared to floating gate memories, resulting in lower peripheral voltages and consequently a lower die cost. While write/erase voltages can be lowered from ±9V to around ±6V, these voltages are still elevated compared to the chip supply voltage. The manufacturing process is simplified, however, because some features of the peripheral and core or input/output transistors can be shared. Thin film storage NVM has been in production for niche markets such as radiation-hard electronics, Smart Cards, and others. For both write and erase, the tunnel effect has been employed, where the application of a vertical voltage to a stack of oxide/nitride/oxide causes charge to move into or out of the nitride, resulting in a uniformly charged film.
Recently, a more compact method of charge storage has been developed in which a localized packet of charge is transported into the nitride film with hot carrier injection, resulting in more compact bitcells. Two complementary methods of write and erase can be employed: either, two charges (and two bits of information) can be stored in one bitcell while maintaining a high peripheral voltage of ±9V; or, one charge can be stored with a lower peripheral voltage (±6V) in a very compact bitcell.
In addition to charge storage in a silicon dioxide/silicon nitride/silicon dioxide stack, researchers have recently succeded in forming small, 50 angstrom-thick silicon balls, called nanocrystals, 10,000 times smaller than a human hair. The nanocrystals are embedded between 50-100 angstrom -thick silicon dioxide layers at a 50 angstrom spacing such that no conduction can occur from between the nanocrystals. The device structure resembles a conventional floating gate bitcell in which the floating gate has been cho pped into many small pieces. Write/erase mechanisms similar to the ones used in floating gate memories can be applied.
Since both floating gate and thin film storage NVM have write and erase times which are orders of magnitude longer than typical read access times, and since the number of write/erase cycles is limited to a range between 10,000-100,000, these embedded memories cannot be used to replace SRAM or embedded DRAM.
The holy grail of embedded NVM design has always been to create a non-volatile memory which, for similar die size, process complexity, and reliability can replace conventional SRAM or embedded DRAM. For these applications, write and erase times have to be in the 10's of nano-seconds instead of the 1-1000 micro-second range. The most advanced of these memories are magnetic RAM (MRAM), ferro-electric RAM, (FeRAM), and phase-change or "ovonic unified" memory (OUM or PRAM).
None of these revolutionary embedded NVM's is currently in mass production for applications de manding the highest reliability such as engine controllers, but the growing disparity between core and peripheral voltages at the 130nm and 90nm technology nodes increases the motivation to productize first thin film storage NVM and ultimately revolutionary NVM.
The key challenge for productizing a revolutionary embedded NVM has always been that new materials and methods of operation have to be developed while attempting to intercept products fabricated with scaled conventional embedded NVM technology.
| Schematics of floating gate and thin-film storage-based embedded nonvolatile memory bitcells. Depending on the charge stored inside the gate dielectric of a MOS field-effect transistor, the threshold voltage can be very high (off state) or so low that a read voltage applied to the polys ilicon gate can turn on the transistor (on state). |
Source: Motorola Inc.
To justify the increased schedule risk of any revolutionary technology for SoC productization, a significant increase in the feature set is mandatory, ideally accompanied by a "killer application" which cannot be met with any other technology.
It is expected that at the 90nm technology node thin film storage based memory concepts will emerge to support traditional embedded NVM applications more cost-effectively, leading to a more balanced replacement of conventional Flash EEPROM.
Revolutionary concepts will also be explored, with MRAM, FeRAM, and PRAM being most likely to succeed in certain applications where the SoC can be segmented more optimally taking advantage of the increased feature set.
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