Merged-logic-type embedded DRAM suits high-performance SoCs

As a reliable, proven and compiled memory technology, embedded SRAM is often the default choice for embedded memory solutions. Unfortunately, embedded SRAM has drawbacks that become an issue as feature sizes shrink and integration increases. First, embedded SRAM is not dense because it requires the conventional six transistors to form a single bit cell. Reasonable SRAM sizes are thus less than 1 megabit. Second, embedded SRAM dissipates more power than alternative technologies. Embedded SRAM is also proving to be increasingly susceptible to soft errors caused by high-energy particles.

Alternatively, embedded DRAM provides higher density, lower power consumption and lower soft error rate (SER). Several types of DRAM technology have been developed, and they fall into three categories: commodity DRAM, standard logic (SL) and merged logic (ML). The first type is the technology used to fabricate discrete commodity DRAM, while both the SL and ML types use standard CMOS.

The difference between SL- and ML-type embedded DRAM is in the DRAM capacitor structures. SL-type DRAM implements planar capacitors (between the well and gate-poly). The ML type uses DRAM capacitors similar to the commodity DRAM type, but the fabrication technology must be completely different from that of commodity DRAM. Both DRAM-type and ML-type embedded DRAM use one of two alternative capacitor structures: stacked or trench.

The commodity DRAM process offers high memory density resulting from its small memory cell size. However, this type of DRAM does not suit high-speed applications because of its lower transistor performance and limited number of metal layers. Some DRAM-type processes can enhance transistor performance, but with a huge number of additional process steps.

Compared to the ML type, SL-type embedded DRAM requires a smaller number of additional process steps to implement the DRAM capacitors. The memory density is lower than that of the commodity DRAM and ML types, however, because the SL-type planar capacitors take up a large area. Pushing up the SL-type capacitance to minimize the refresh frequency, also increases the area penalty. In addition to shorter data retention time, sma ller storage capacitance makes the cell somewhat more susceptible to soft errors, similar to those seen in embedded SRAM.

The ML-type embedded DRAM offers several advantages. First, the process can fabricate high-performance logic transistors. Second, the large ML-type capacitance achieves reasonable data retention time and low soft error rates. Third, The ML type has higher memory density and lower power consumption than the other types.

Cost, compatibility issues

The major disadvantage of the ML type is its higher cost resulting from the additional process steps needed to make the bit cells. Conventional ML-type embedded DRAM also has several other disadvantages. For one, the conventional process is not CMOS compatible. It thus requires wafers to go back and forth between separate CMOS and DRAM fabrication lines, lengthening turnaround time, reducing yields and increasing costs. The conventional ML type's random-access speed is also slower than that of SRAM, and it is difficult to optimize the chip's floor-plan and signal-integrity characteristics because layout is inflexible. Specifically, the orientation of the DRAM cell is fixed and routing over the DRAM has not been possible.

The conventional process is not the end of the ML-type story, however. It turns out that ML-type embedded DRAM can be fabricated in a different way that suits SoC requirements for modest to large amounts of embedded memory. With these changes, the ML-type process becomes compatible with standard CMOS. Low-temperature MIM capacitor technology secures high logic transistor performance and overall yield. With new bit-cell materials, extremely high-speed designs have been characterized to offer up to 314-MHz random access at 1.2 volts in 0.13-micron technologies, yet density is more than five times that of embedded SRAM. The new ML-type DRAM's large, isolated vertical capacitor makes it nearly immune to soft error upset. Finally, the DRAM macros are orientation-free, and metal rou ting over the DRAM macros is allowed. This flexibility allows you to choose the optimum chip layout.

In this SoC era, 50 percent or more of the die will consist of embedded memory. Before recent embedded DRAM advancements, most of this memory resided off-chip because embedded DRAM failed to meet the design requirements for SRAM functionality with DRAM area and power capabilities. Along with a high level of noise isolation among different DRAM blocks, new embedded DRAM capabilities can provide SRAM functionality with DRAM area and power.

Nonvolatile memory devices can be valuable options for SoC chips. Among the various types of proposed nonvolatile memory are ferroelectric RAM (FeRAM), magnetic random access memory (MRAM), Ovonic Unified Memory (OUM) and E2PROM. The criteria for judging whether any of these technologies is suitable for SoCs are the same as for embedded DRAM: CMOS compatibility, fewer additional process steps that are not exclusive to embedded DRAM and byte read/write capabil ity.

Before becoming viable for SoCs, OUM needs to conquer the high thermal budget issue (greater than 600°C for the write operation). The thermal budget is also one of the critical issues for MRAM. MRAM's memory structure requires lower thermal conditions (around 200 to 300°C), but the copper interconnect requires about 400°C. Additionally, the MRAM sense amplifier must improve so that it can sense smaller differences in magnetic resistivities (20 to 40 percent).

Conventional FeRAM has the same thermal budget issue as MRAM and it is not suitable for SoCs. However, NEC Electronics has developed a new FeRAM for SoCs that offers a low-temperature ferroelectric device that can be formed over the top metal wiring.

Nonvolatile embedded memory devices are useful, but the primary need in today's SoCs is for a cost-effective, general-purpose embedded memory that has the speed to replace SRAM and the density to keep costs reasonable.

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