Process experts map path to 90-nm memory

Process experts map path to 90-nm memory
By Chappell Brown, EE Times
March 18, 2003 (12:57 p.m. EST)
URL: http://www.eetimes.com/story/OEG20030317S0050

Semiconductor memory, with its simple, regular structure, has traditionally been the arena in which the problems posed by the next VLSI generation have been explored and resolved. But the memory game has acquired a new set of rules and requirements with the system-on-chip generation. The high capacity of SoCs means that many different circuit types need to coexist on one chip, and that implies a common process for logic, memory and possibly analog circuitry as well.

Although memory is just as fundamental to system design today as it has always been, it is just one more circuit block on a chip, and process engineers can't afford to maximize memory density and performance at the expense of other on-chip circuits. The various memory types-dynamic RAM, static RAM, floating-gate E2PROM and basic ROM-all have unique sets of abilities and performance parameters. And they have been optimized in isolation from one another, so there is no guarantee that their best properties will be retained if they end up on the same chip.

In this installment of the Silicon Engineering In Focus series, we present the thinking of five major semiconductor makers on what will be the optimal memory solution as SoC technology races toward the 90-nanometer node. A piece from Peter Rickert, director of ASP platform management at Texas Instruments Inc., explaining a new type of integrated nonvolatile memory based on ferroelectric capacitors, appears here in print, while engineers at IBM, Motorola, NEC Electronics America and Toshiba America Electronic Components offer online, exclusive looks at their latest efforts.

Frank R. Ramsay at Toshiba America's System LSI Group argues in his online contribution that the entire process integration problem needs to be solved, not just DRAM or other memory integration processes. Toshiba engineers have devised a comprehensive circuit integration process that begins with deep-trench DRAM capacitor definition and then adds proce ss steps designed to include virtually any type of circuit: ROM, SRAM, logic and mixed-signal circuit types can all be included in a modular fashion. To bump up yield, Toshiba supplies ROM macros that can be specified by the customer, and includes redundant SRAM cells that are used to repair memory circuits after manufacture.

IBM Corp. is striving to maximize the speed and flexibility of embedded DRAM using a predesigned library of DRAM memory modules. These can be blended to create any required configuration. Part of the company's strategy is to offer 1-Mbit standard blocks that can be interleaved in a parallel-addressing scheme to build large memory arrays with fast data access.

Motorola Inc. engineers tackle the nonvolatile aspects of embedded-memory technology, arguing that novel materials such as ferroelectric capacitors, magnetic RAM and Ovonic memory types will finally come into their own in the 90-nm generation.

High-speed integration

Finally, memory engineers from NEC Electronics America Inc. tackle the speed issue with a DRAM process that makes a close fit with CMOS logic. In fact, their process allows them to build DRAM memory and CMOS logic side by side in the same process, leading to high-speed memory integration wherever it is needed. Called merged-logic embedded DRAM, the approach claims to offer both the capacity and speed required in high-end applications.

The theme that emerges from these articles is the central role that DRAM will play in solving the SoC memory dilemma.

Each of the strategies for blending DRAM structures with logic circuits starts at the same point: Deep-trench capacitors are first built on the substrate and the resulting structure is planarized. At that point, additional interconnect to link the array of capacitors can be built as part of further circuit definition. This strategy gets the incompatible segment of DRAM definition-due mainly to high-temperature processing-out of the way.

Although not as fast as SRAM a nd lacking the data retention capabilities of nonvolatile memory types, DRAM nevertheless has the best chance of integrating itself with diverse circuit types in a common process. Even TI's ferrroelectric RAM is basically a DRAM in which the capacitor material has been replaced with new material to introduce nonvolatility. With further tweaking, DRAM may one day evolve into the ideal semiconductor memory: fast, dense, low power and nonvolatile.

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