By Madhumita Sanyal, Sr. Staff Technical Marketing Manager, Synopsys
EETimes (February 28, 2022)
Because of the data explosion and increasing bandwidth for high-performance computing (HPC), we are seeing PCI Express (PCIe) data rates moving from 32G (PCIe 5.0) to 64G (PCIe 6.0). In addition, since NRZ no longer supports the higher data rates, PCIe 6.0 is moving to PAM-4 signaling. The higher volumes of data and faster data movement for computing, networking, and storage are pushing performance and latency optimization to the highest levels. Figure 1 shows the inside of a server box in a server rack unit, illustrating the necessary shift from PCIe 5.0 data rates to PCIe 6.0 data rates for network interface cards (NICs), SSDs and overall chip-to-chip connectivity, as well as alignment with network speeds from 400G to 800G to 1.6T Ethernet. A server box has a fixed dimension; hence it maintains similar footprint and form factor. PCIe 6.0 can’t grow bigger and maintains similar latency to PCIe 5.0. Higher power is needed to push the data at higher speeds through CPUs, GPUs, SSDs, accelerators, and NICs. However, the entire chassis can heat up and require cooling to keep the components at a safe operating temperature, which can consume additional power. Hence, power consumption, system latency, and area challenges become key parameters to consider, forcing SoC designers to re-architect their HPC designs. This article outlines how designers can overcome the power, performance, area and latency challenges of PCIe 6.0 designs using pre-validated and comprehensive PCIe IP solutions.
To achieve best performance, PCIe systems are optimized with faster clocks, which means increased latency because design changes can add pipelining to meet timing. Area and power impacts are also added. Because of these reasons SoC architectures are going through a shift. SoC designers need to find a balance between faster performance with lowest latency while minimizing area and power. Optimizing the 4 parameters – power, performance, area and latency – in a PCIe 6.0 design implementation requires designers to make tradeoff analysis, which is time consuming.
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